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| ? 2007-2012 microchip technology inc. ds70283k-page 1 dspic33fj32mc202/204 and dspic33fj16mc304 operating conditions ? 3.0v to 3.6v, -40oc to +150oc, dc to 20 mips ? 3.0v to 3.6v, -40oc to +125oc, dc to 40 mips core: 16-bit dspic33f cpu ? code-efficient (c and assembly) architecture ? two 40-bit wide accumulators ? single-cycle (mac/mpy) with dual data fetch ? single-cycle mixed-sign mul plus hardware divide clock management ? 2% internal oscillator ? programmable plls and oscillator clock sources ? fail-safe clock monitor (fscm) ? independent watchdog timer (wdt) ? fast wake-up and start-up power management ? low-power management modes (sleep, idle, doze) ? integrated power-on reset and brown-out reset ? 1.35 ma/mhz dynamic current (typical) ? 55 a ipd current (typical) high-speed pwm ? up to four pwm pairs with independent timing ? dead time for rising and falling edges ? 12.5 ns pwm resolution ? pwm support for: - dc/dc, ac/dc, invert ers, pfc, lighting - bldc, pmsm, acim, srm ? programmable fault inputs ? flexible trigger configurations for adc conversions advanced analog features ? adc module: - configurable as 10-bit, 1.1 msps with four s&h or 12-bit, 500 ksps with one s&h ? six analog inputs on 28-pin devices and up to nine analog inputs on 44-pin devices ? flexible and independent adc trigger sources timers/output compare/input capture ? three 16-bit timers/counters. can pair up two to make one 32-bit. ? two output capture modules configurable as timers/counters ? four input capture modules ? peripheral pin select (pps) to allow function remap communication interfaces ? one uart module (10 mbps) ? with support for lin 2.0 protocols and irda ? ? one 4-wire spi module (15 mbps) ? one i 2 c? module (up to 1 mbaud) with smbus support ? pps to allow function remap input/output ? sink/source up to 10 ma (pin specific) for stan- dard voh/vol, up to 16 ma (pin specific) for non-standard voh1 ? 5v-tolerant pins ? selectable open drain, pull-ups, and pull-downs ? up to 5 ma overvoltage clamp current ? external interrupts on all i/o pins qualification and class b support ? aec-q100 revg (grade 0 -40oc to +150oc) ? class b safety library, iec 60730 debugger development support ? in-circuit and in-application programming ? two program and two complex data breakpoints ? ieee 1149.2-compatible (jtag) boundary scan ? trace and run-time watch packages type spdip soic ssop qfn-s qfn tqfp pin count 28 28 28 28 44 44 contact lead/pitch .100'' 1.27 0.65 0.65 0.65 0.80 i/o pins 21 21 21 21 35 35 dimensions 1.365x.285x.135'' 17.9xx7.50x2.05 10. 2x5.3x1.75 6x6x0.9 8x8x0.9 10x10x1 note: all dimensions are in millimeters (mm) unless specified. 16-bit digital signal controllers (up to 32 kb flash and 2 kb sram) with motor control and advanced analog
dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 2 ? 2007-2012 microchip technology inc. ds pic33fj32mc202/204 and dspic33fj16mc304 product families the device names, pin counts, memory sizes and peripheral availability of each device are listed below. the following pages show their pinout diagrams. table 1: dspic33fj32mc202/204 and dspic33fj16mc304 controller families device pins program flash memory (kbyte) ram (kbyte) remappable peripherals 10-bit/12-bit adc i 2 c? i/o pins packages remappable pins 16-bit timer input capture output compare standard pwm motor control pwm quadrature encoder interface uart external interrupts (3) spi dspic33fj32mc202 28 32 2 16 3 (1) 426ch (2) 2ch (2) 1 1 3 1 1adc, 6 ch 121 spdip soic ssop qfn-s dspic33fj32mc204 44 32 2 26 3 (1) 426ch (2) 2ch (2) 1 1 3 1 1adc, 9 ch 135qfn tqfp dspic33fj16mc304 44 16 2 26 3 (1) 426ch (2) 2ch (2) 1 1 3 1 1adc, 9 ch 135qfn tqfp note 1: only two out of three timers are remappable. 2: only pwm fault inputs are remappable. 3: only two out of three interrupts are remappable. ? 2007-2012 microchip technology inc. ds70283k-page 3 dspic33fj32mc202/204 and dspic33fj16mc304 pin diagrams dspic33fj32mc202 mclr v ss v dd an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 av dd av ss pged1/an2/c2in-/rp0 (1) /cn4/rb0 pgec3/ascl1/rp6 (1) /cn24/rb6 sosco/t1ck/cn0/ra4 sosci/rp4 (1) /cn1/rb4 v ss osc2/clko/cn29/ra3 osc1/clki/cn30/ra2 v cap int0/rp7/cn23/rb7 tdo/pwm2l1/sda1/rp9 (1) /cn21/rb9 tck/pwm2h1/scl1/rp8 (1) /cn22/rb8 an5/rp3 (1) /cn7/rb3 an4/rp2 (1) /cn6/rb2 pgec1/an3/c2in+/rp1 (1) /cn5/rb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rp14 (1) /cn12/rb14 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pged2/tdi/pwm1h3/rp10 (1) /cn16/rb10 pgec2/tms/pwm1l3/rp11 (1) /cn15/rb11 pged3/asda1/rp5 (1) /cn27/rb5 28-pin spdip, soic, ssop 28-pin qfn-s (2) 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 dspic33fj32mc202 5 4 mclr v ss v dd an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 av dd av ss pged1/emud1/an2/c2in-/rp0 (1) /cn4/rb0 pgec3/emuc3/ascl1/rp6 (1) /cn24/rb6 sosco/t1ck/cn0/ra4 sosci/rp4/cn1/rb4 v ss osc2/clko/cn29/ra3 osc1/clki/cn30/ra2 v cap int0/rp7 (1) /cn23/rb7 tdo/pwm2l1/sda1/rp9 (1) /cn21/rb9 tck/pwm2h1/scl1/rp8 (1) /cn22/rb8 an5/rp3 (1) /cn7/rb3 an4/rp2 (1) /cn6/rb2 pgec1/emuc1/an3/c2in+/rp1 (1) /cn5/rb1 pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rp14 (1) /cn12/rb14 pwm1l2/rp13 (1) /cn13/rb13 pwm1h2/rp12 (1) /cn14/rb12 pged2/emud2/tdi/pwm1h3/rp10 (1) /cn16/rb10 pgec2/emuc2/tms/pwm1l3/rp11 (1) /cn15/rb11 pged3/emud3/asda1/rp5 (1) /cn27/rb5 note 1: the rpn pins can be used by any remappable peripheral. see ta b l e 1 for the list of available peripherals. 2: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. = pins are up to 5v tolerant = pins are up to 5v tolerant dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 4 ? 2007-2012 microchip technology inc. pin diagrams (continued) 44-pin qfn (2) 44 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 6 22 33 34 dspic33fj32mc204 pgec1/emuc1/an3/c2in+/rp1 (1) /cn5/rb1 pged1/emud1/an2/c2in-/rp0 (1) /cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/ra10 av dd av ss pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rp14 (1) /cn12/rb14 tck/ra7 scl1/rp8 (1) /cn22/rb8 int0/rp7/cn23/rb7 pgec3/emuc3/ascl1/rp6 (1) /cn24/rb6 pged3/emud3/asda1/rp5 (1) /cn27/rb5 v dd tdi/ra9 sosco/t1ck/cn0/ra4 v ss rp21 (1) /cn26/rc5 rp20 (1) /cn25/rc4 rp19 (1) /cn28/rc3 pwm1h2/rp12 (1) /cn14/rb12 pgec2/emuc2/pwm1l3/rp11 (1) /cn15/rb11 pged2/emud2/pwm1h3/rp10 (1) /cn16/rb10 v cap v ss rp25/cn19/rc9 rp24/cn20/rc8 pwm2l1/rp23 (1) /cn17/rc7 pwm2h1/rp22 (1) /cn18/rc6 sda1/rp9 (1) /cn21/rb9 pwm1l2/rp13 (1) /cn13/rb13 an4/rp2 (1) /cn6/rb2 an5/rp3 (1) /cn7/rb3 an6/rp16 (1) /cn8/rc0 an7/rp17 (1) /cn9/rc1 an8/rp18 (1) /cn10/rc2 sosci/rp4 (1) /cn1/rb4 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 tdo/ra8 dspic33fj16mc304 = pins are up to 5v tolerant note 1: the rpn pins can be used by any remappable peripheral. see ta b l e 1 for the list of available peripherals. 2: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. ? 2007-2012 microchip technology inc. ds70283k-page 5 dspic33fj32mc202/204 and dspic33fj16mc304 pin diagrams (continued) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 37 scl1/rp8 (1) /cn22/rb8 int0/rp7 (1) /cn23/rb7 pgec3/emuc3/ascl1/rp6 (1) /cn24/rb6 pged3/emud3/asda1/rp5 (1) /cn27/rb5 v dd tdi/ra9 sosco/t1ck/cn0/ra4 v ss rp21 (1) /cn26/rc5 rp20 (1) /cn25/rc4 rp19/ (1) cn28/rc3 pgec1/emuc1/an3/c2in+/rp1 (1) /cn5/rb1 pged1/emud1/an2/c2in-/rp0 (1) /cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/ra10 av dd av ss pwm1l1/rp15 (1) /cn11/rb15 pwm1h1/rp14 (1) /cn12/rb14 pwm1h2/rp12 (1) /cn14/rb12 pgec2/emuc2/pwm1l3/rp11 (1) /cn15/rb11 pged2/emud2/pwm1h3/rp10 (1) /cn16/rb10 v cap v ss rp25 (1) /cn19/rc9 rp24 (1) /cn20/rc8 pwm2l1/rp23 (1) /cn17/rc7 pwm2h1/rp22 (1) /cn18/rc6 sda1/rp9 (1) /cn21/rb9 an4/rp2 (1) /cn6/rb2 an5/rp3 (1) /cn7/rb3 an6/rp16 (1) /cn8/rc0 an7/rp17 (1) /cn9/rc1 an8/rp18 (1) /cn10/rc2 sosci/rp4 (1) /cn1/rb4 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 tdo/ra8 44-pin tqfp pwm1l2/rp13 (1) /cn13/rb13 tck/ra7 dspic33fj32mc204 dspic33fj16mc304 note 1: the rpn pins can be used by any remappable peripheral. see ta b l e 1 for the list of available peripherals. = pins are up to 5v tolerant dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 6 ? 2007-2012 microchip technology inc. table of contents dspic33fj32mc202/204 and dspic33fj16mc304 product families..................................................................... ............................. 2 1.0 device overview ............................................................................................................. ............................................................. 9 2.0 guidelines for getting started with 16 -bit digital signal controllers ....................................................... ................................... 13 3.0 cpu......................................................................................................................... ................................................................... 17 4.0 memory organization ......................................................................................................... ........................................................ 29 5.0 flash program memory ........................................................................................................ ...................................................... 55 6.0 resets ..................................................................................................................... .................................................................. 61 7.0 interrupt controller ........................................................................................................ ............................................................. 71 8.0 oscillator configuration .................................................................................................... ........................................................ 101 9.0 power-saving features....................................................................................................... ..................................................... 111 10.0 i/o ports .................................................................................................................. ................................................................. 117 11.0 timer1 ..................................................................................................................... ................................................................. 143 12.0 timer2/3 feature .......................................................................................................... ............................................................ 147 13.0 input capture.............................................................................................................. .............................................................. 151 14.0 output compare............................................................................................................. .......................................................... 155 15.0 motor control pwm module ................................................................................................... .................................................. 159 16.0 quadrature encoder interface (qei) module .................................................................................. ......................................... 173 17.0 serial peripheral interface (spi).......................................................................................... ..................................................... 179 18.0 inter-integrated circuit? (i 2 c?) ............................................................................................................................ .................. 185 19.0 universal asynchronous rece iver transmitter (uart) ......................................................................... .................................. 193 20.0 10-bit/12-bit analog-to-digital converter (adc) ............................................................................ ........................................... 199 21.0 special features ........................................................................................................... ........................................................... 211 22.0 instruction set summary .................................................................................................... ...................................................... 219 23.0 development support........................................................................................................ ....................................................... 227 24.0 electrical characteristics ................................................................................................. ......................................................... 231 25.0 high temperature electrical characteristics ................................................................................ ............................................ 281 26.0 dc and ac device characteristics graphs.................................................................................... .......................................... 291 27.0 packaging information...................................................................................................... ........................................................ 295 appendix a: revision history................................................................................................... .......................................................... 309 index .......................................................................................................................... ....................................................................... 321 the microchip web site ......................................................................................................... ............................................................ 325 customer change notification service ........................................................................................... ................................................... 325 customer support ............................................................................................................... ............................................................... 325 reader response ................................................................................................................ .............................................................. 326 product identification system.................................................................................................. ........................................................... 327 ? 2007-2012 microchip technology inc. ds70283k-page 7 dspic33fj32mc202/204 and dspic33fj16mc304 to our valued customers it is our intention to provide our valued cu stomers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publicati ons to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we wel- come your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/docum entation issues become known to us, we will publish an errata sheet. t he errata will s pecify the revisi on of silicon and revision of doc ument to which it applies. to determine if an errata sheet exists for a partic ular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 8 ? 2007-2012 microchip technology inc. referenced sources this device data sheet is based on the following individual chapters of the ?dspic33f/pic24h family reference manual? . these documents should be considered as the general re ference for the operation of a particular module or device feature. ? section 1. ?introduction? (ds70197) ? section 2. ?cpu? (ds70204) ? section 3. ?data memory? (ds70202) ? section 4. ?program memory? (ds70202) ? section 5. ?flash programming? (ds70191) ? section 7. ?oscillator? (ds70186) ? section 8. ?reset? (ds70192) ? section 9. ?watchdog timer and power-saving modes? (ds70196) ? section 10. ?i/o ports? (ds70193) ? section 11. ?timers? (ds70205) ? section 12. ?input capture? (ds70198) ? section 13. ?output compare? (ds70209) ? section 14. ?motor control pwm? (ds70187) ? section 15. ?quadrature encoder interface (qei)? (ds70208) ? section 16. ?analog-to-digital converter (adc)? (ds70183) ? section 17. ?uart? (ds70188) ? section 18. ?serial peri pheral interface (spi)? (ds70206) ? section 19. ?inter-integrated circuit? (i 2 c?)? (ds70195) ? section 23. ?codeguard? security? (ds70199) ? section 25. ?device configuration? (ds70194) ? section 32. ?interrupts (part iii)? (ds70214) note 1: to access the documents listed below, browse to the documentation section of the dspic33fj32mc204 product page of the microchip web site ( www.microchip.com ) or select a family reference manual section from the following list. in addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. ? 2007-2012 microchip technology inc. ds70283k-page 9 dspic33fj32mc202/204 and dspic33fj16mc304 1.0 device overview this document contains devic e-specific information for the following digital signal controller (dsc) devices: ? dspic33fj32mc202 ? dspic33fj32mc204 ? dspic33fj16mc304 the dspic33f devices contain extensive digital signal processor (dsp) functionality with a high performance 16-bit microcontroller (mcu) architecture. figure 1-1 shows a general block diagram of the core and peripheral modules in the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. table 1-1 lists the functions of the various pins shown in the pinout diagrams. note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 devices. it is not intended to be a comprehensive refer- ence source. to complement the infor- mation in this data sheet, refer to the ?dspic33f/pic24h family reference manual? . please see the microchip web site ( www.microchip.com ) for the latest dspic33f/pic24h family reference manual sections. 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 10 ? 2007-2012 microchip technology inc. figure 1-1: dspic33fj32mc202/204 and dspic33fj16mc304 block diagram 16 osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset precision reference band gap frc/lprc oscillators regulator voltage v cap ic1,2,7,8 i2c1 porta note: not all pins or features are implement ed on all device pinout configurations. see ? pin diagrams ? for the specific pins and features present on each device. instruction decode and control pch pcl 16 program counter 16-bit alu 23 23 24 23 instruction reg pcu 16 x 16 w register array rom latch 16 ea mux 16 16 8 interrupt controller psv and table data access control block stack control logic loop control logic data latch address latch address latch program memory data latch literal data 16 16 16 16 data latch address latch 16 x ram y ram y data bus x data bus dsp engine divide support 16 control signals to various blocks adc1 timers portb address generator units 1-3 cnx uart1 oc/ pwm1-2 qei pwm 2 ch pwm 6 ch remappable pins 16 portc spi1 ? 2007-2012 microchip technology inc. ds70283k-page 11 dspic33fj32mc202/204 and dspic33fj16mc304 table 1-1: pinout i/o descriptions pin name pin type buffer type pps description an0-an8 i analog no analog input channels. clki clko i o st/cmos ? no no external clock source input. alwa ys associated with osc1 pin function. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1 osc2 i i/o st/cmos ? no no oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. sosci sosco i o st/cmos ? no no 32.768 khz low-power oscillator crystal input; cmos otherwise. 32.768 khz low-power oscillator crystal output. cn0-cn30 i st no change notification inputs. can be software programmed for internal weak pull-ups on all inputs. ic1-ic2 ic7-ic8 i i st st yes yes capture inputs 1/2. capture inputs 7/8. ocfa oc1-oc2 i o st ? yes yes compare fault a input (for compare channels 1 and 2). compare outputs 1 through 2. int0 int1 int2 i i i st st st no yes yes external interrupt 0. external interrupt 1. external interrupt 2. ra0-ra4 ra7-ra10 i/o st no no porta is a bidirectional i/o port. rb0-rb15 i/o st no portb is a bidirectional i/o port. rc0-rc9 i/o st no portc is a bidirectional i/o port. t1ck t2ck t3ck i i i st st st no yes yes timer1 external clock input. timer2 external clock input. timer3 external clock input. u1cts u1rts u1rx u1tx i o i o st ? st ? yes yes yes yes uart1 clear to send. uart1 ready to send. uart1 receive. uart1 transmit. sck1 sdi1 sdo1 ss1 i/o i o i/o st st ? st yes yes yes yes synchronous serial clo ck input/output for spi1. spi1 data in. spi1 data out. spi1 slave synchronization or frame pulse i/o. scl1 sda1 ascl1 asda1 i/o i/o i/o i/o st st st st no no no no synchronous serial clock input/output for i2c1. synchronous serial data input/output for i2c1. alternate synchronous serial clock input/output for i2c1. alternate synchronous serial data input/output for i2c1. tms tck tdi tdo i i i o st st st ? no no no no jtag test mode select pin. jtag test clock input pin. jtag test data input pin. jtag test data output pin. legend: cmos = cmos compatible input or ou tput; analog = analog input; p = power st = schmitt trigger input with cmos levels; o = output; i = input pps = peripheral pin select dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 12 ? 2007-2012 microchip technology inc. indx qea qeb updn i i i o st st st cmos yes yes yes yes quadrature encoder index pulse input. quadrature encoder phase a input in qei mode. auxiliary timer external clo ck/gate input in timer mode. quadrature encoder phase a input in qei mode. auxiliary timer external clo ck/gate input in timer mode. position up/down counter direction state. flta1 pwm1l1 pwm1h1 pwm1l2 pwm1h2 pwm1l3 pwm1h3 flta2 pwm2l1 pwm2h1 i o o o o o o i o o st ? ? ? ? ? ? st ? ? yes no no no no no no yes no no pwm1 fault a input. pwm1 low output 1. pwm1 high output 1. pwm1 low output 2. pwm1 high output 2. pwm1 low output 3. pwm1 high output 3. pwm2 fault a input. pwm2 low output 1. pwm2 high output 1. pged1 pgec1 pged2 pgec2 pged3 pgec3 i/o i i/o i i/o i st st st st st st no no no no no no data i/o pin for programming/debugging communication channel 1. clock input pin for programming/debugging communication channel 1. data i/o pin for programming/debugging communication channel 2. clock input pin for programming/debugging communication channel 2. data i/o pin for programming/debugging communication channel 3. clock input pin for programming/debugging communication channel 3. mclr i/p st no master clear (reset) input. this pin is an active-low reset to the device. avdd p p no positive supply for analog modules. this pin must be connected at all times. avss p p no ground reference for analog modules. v dd p ? no positive supply for peripheral logic and i/o pins. v cap p ? no cpu logic filter capacitor connection. v ss p ? no ground reference for logic and i/o pins. v ref + i analog no analog voltage reference (high) input. v ref - i analog no analog voltage reference (low) input. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or ou tput; analog = analog input; p = power st = schmitt trigger input with cmos levels; o = output; i = input pps = peripheral pin select ? 2007-2012 microchip technology inc. ds70283k-page 13 dspic33fj32mc202/204 and dspic33fj16mc304 2.0 guidelines for getting started with 16-bit digital signal controllers 2.1 basic connection requirements getting started with the dspic33fj32mc202/204 and dspic33fj16mc304 family of 16-bit digital signal controllers (dscs) requires attention to a minimal set of device pin connections before proceeding with development. the following is a list of pin names, which must always be connected: ? all v dd and v ss pins (see section 2.2 ?decoupling capacitors? ) ? all av dd and av ss pins (even if the adc module is not used) (see section 2.2 ?decoupling capacitors? ) ?v cap (see section 2.3 ?cpu logic filter capacitor connection (v cap )? ) ?mclr pin (see section 2.4 ?master clear (mclr) pin? ) ? pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 ?icsp pins? ) ? osc1 and osc2 pins when external oscillator source is used (see section 2.6 ?externa l oscillator pins? ) additionally, the following pins may be required: ?v ref +/v ref - pins used when external voltage reference for adc module is implemented 2.2 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd , v ss , av dd and av ss is required. consider the following criteria when using decoupling capacitors: ? value and type of capacitor: recommendation of 0.1 f (100 nf), 10-20v. this capacitor should be a low-esr and have a resonance frequency in the range of 20 mhz and higher. it is recommended that ceramic capacitors be used. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. ? handling high frequency noise: if the board is experiencing high frequency noise, upward of tens of mhz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing pcb track inductance. note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the ?dspic33f/pic24h fa mily reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the av dd and av ss pins must be connected independent of the adc voltage reference source. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 14 ? 2007-2012 microchip technology inc. figure 2-1: recommended minimum connection 2.2.1 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including dscs to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that con- nects the power supply sour ce to the device, and the maximum current drawn by the device in the applica- tion. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 f to 47 f. 2.3 cpu logic filter capacitor connection (v cap ) a low-esr (<5 ohms) capacitor is required on the v cap pin, which is used to stabilize the voltage regulator output voltage. the v cap pin must not be connected to v dd , and must have a capacitor between 4.7 f and 10 f, 16v connected to ground. the type can be ceramic or tantalum. refer to section 24.0 ?electrical characteristics? for additional information. the placement of this capacitor should be close to the v cap . it is recommended that the trace length not exceed one-quarter inch (6 mm). refer to section 21.2 ?on-chip voltage regulator? for details. 2.4 master clear (mclr ) pin the mclr pin provides for two specific device functions: ? device reset ? device programming and debugging during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adve rsely affected. therefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as shown in figure 2-2 , it is recommended that capacitor c is isolated from the mclr pin during programming and debugging operations. place the components shown in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections dspic33f v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic c r v dd mclr 0.1 f ceramic v cap l1 (1) r1 10 f tantalum note 1: as an option, instead of a hard-wired connection, an inductor (l1) can be substituted between v dd and av dd to improve adc noise rejection. the inductor impedance should be less than 1 and the inductor capacity greater than 10 ma. where: f f cnv 2 ------------- - = f 1 2 lc () ----------------------- = l 1 2 fc () --------------------- ?? ?? 2 = (i.e., adc conversion rate/2) note 1: r 10 k is recommended. a suggested starting value is 10 k . ensure that the mclr pin v ih and v il specifications are met. 2: r1 470w will limit any current flowing into mclr from the external capacitor c, in the event of mclr pin breakdown, due to elec- trostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. c r1 (2) r (1) v dd mclr dspic33f jp ? 2007-2012 microchip technology inc. ds70283k-page 15 dspic33fj32mc202/204 and dspic33fj16mc304 2.5 icsp pins the pgecx and pgedx pins are used for in-circuit serial programming (icsp) and debugging purposes. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the ic sp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to t he ac/dc characteristics and timing requirements information in the respective device flash programming spec ification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. ensure that the ?communication channel select? (i.e., pgecx/pgedx pins) programmed into the device matches the physical con nections for the icsp to mplab ? icd 3 or mplab real ice? in-circuit emu- lator. for more information on mplab icd 3 or mplab real ice? in-circuit emulator connection requirements, refer to the following documents that are available on the microchip web site. ? ?using mplab ? icd 3? (poster) ds51765 ? ?mplab ? icd 3 design advisory? ds51764 ? ?mplab ? real ice? in-circuit emulator user?s guide? ds51616 ? ?using mplab ? real ice? in-circuit emulator? (poster) ds51749 2.6 external oscillator pins many dscs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 8.0 ?oscillator configuration? for details). the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator circuit close to t he respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board wher e the crystal is placed. a suggested layout is shown in figure 2-3 . figure 2-3: suggested placement of the oscillator circuit 13 main oscillator guard ring guard trace secondary oscillator 14 15 16 17 18 19 20 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 16 ? 2007-2012 microchip technology inc. 2.7 oscillator value conditions on device start-up if the pll of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 8 mhz for start-up with pll enabled. this means that if the external oscillator frequency is outside this range, the application must start-up in frc mode first. the default pll settings after a por with an oscillator frequency outside this range will violate the device operating speed. once the device powers up, the application firmware can initialize the pll sfrs, clkdiv and plldbf to a suitable value, and then perform a clock switch to the oscillator + pll clock source . note that clock switching must be enabled in the device configuration word. 2.8 configuration of analog and digital pins during icsp operations if mplab icd 2, mplab icd 3 or mplab real ice? in-circuit emulator is se lected as a debugger, it auto- matically initializes all of the a/d input pins (anx) as ?digital? pins, by setting all bits in the ad1pcfgl regis- ter. the bits in the registers th at correspond to the a/d pins that are initialized by mplab icd 3 or mplab real ice? in-circuit emulator, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. if your application needs to use certain a/d pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ad1pcfgl register during initialization of the adc module. when mplab icd 3 or mplab real ice? in-circuit emulator is used as a programmer, the user application firmware must correctly configure the ad1pcfgl register. automatic initialization of this register is only done during debugger operation. failure to correctly configure the register(s) will result in all a/d pins being recognized as analog input pins, resulting in the port value being read as a logic ? 0 ?, which may affect user application functionality. 2.9 unused i/os unused i/o pins should be configured as outputs and driven to a logic-low state. alternatively, connect a 1k to 10k resistor between v ss and the unused pins. ? 2007-2012 microchip technology inc. ds70283k-page 17 dspic33fj32mc202/204 and dspic33fj16mc304 3.0 cpu the dspic33fj32mc202/204 and dspic33fj16mc304 cpu module has a 16-bit (data) modified harvard architecture with an enhanced instruction set, including significant support for dsp. the cpu has a 24-bit instruction word with a variable length opcode field. the program counter (pc) is 23 bits wide and addresses up to 4m x 24 bits of user program memory space. the actual amount of program memory implemented varies by device. a single-cycle inst ruction prefetch mechanism is used to help maintain throughput and provides predictable execution. all inst ructions execute in a single cycle, with the exception of in structions that change the program flow, the double-word move ( mov.d ) instruction and the table instructions. overhead-free program loop constructs are supported using the do and repeat instructions, both of which ar e interruptible at any point. the dspic33fj32mc202/204 and dspic33fj16mc304 devices have sixteen, 16-bit working registers in the programmer?s model. each of the working registers can serve as a data, address or address offset register. the 16th working register (w15) operates as a software stack pointer (sp) for interrupts and calls. there are two classes of instruction in the dspic33fj32mc202/204 and dspic33fj16mc304 devices: mcu and dsp. these two instruction classes are seamlessly integrated into a single cpu. the instruction set includes many addressing modes and is designed for optimum c compiler efficiency. for most instructions, the dspic33fj32mc202/204 and dspic33fj16mc304 is capabl e of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per inst ruction cycle. as a result, three parameter instructions can be supported, allowing a + b = c operations to be ex ecuted in a single cycle. a block diagram of the cpu is shown in figure 3-1 , and the programmer?s model for the dspic33fj32mc202/204 and dspic33fj16mc304 is shown in figure 3-2 . 3.1 data addressing overview the data space can be addressed as 32k words or 64 kbytes and is split into two blocks, referred to as x and y data memory. each memory block has its own independent address generation unit (agu). the mcu class of instructions operates solely through the x memory agu, which accesses the entire memory map as one linear data space. certain dsp instructions operate through the x and y agus to support dual operand reads, which splits the data address space into two parts. the x and y data space boundary is device-specific. overhead-free circular buffers (modulo addressing mode) are supported in both x and y address spaces. the modulo addressing removes the software boundary checking overhead for dsp algorithms. furthermore, the x agu circular addressing can be used with any of the mcu class of instructions. the x agu also supports bit-reversed addressing to greatly simplify input or output data reordering for radix-2 fft algorithms. the upper 32 kbytes of the data space memory map can optionally be mapped into program space at any 16k program word boundary defined by the 8-bit program space visibility page register (psvpag). the program-to-data-space mapping feature lets any instruction access program space as if it were data space. 3.2 dsp engine overview the dsp engine features a high-speed 17-bit by 17-bit multiplier, a 40-bit alu, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. the barrel shifter is capable of shifting a 40-bit value up to 16 bits right or left, in a single cycle. the dsp instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. the mac instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two w registers and accumulating and optionally saturating the result in the same cycle. this instruction functionality requires that the ram data space be split for these instructions and linear for all others. data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 2. ?cpu? (ds70204) of the ?dspic33f/pic24h fa mily reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 18 ? 2007-2012 microchip technology inc. 3.3 special mcu features the dspic33fj32mc202/204 and dspic33fj16mc304 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the mcu alu and dsp engine. the multiplier can perform signed, unsigned and mixed-sign multiplication. using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). the dspic33fj32mc202/204 and dspic33fj16mc304 supports 16/16 and 32/16 divide operations, both fractional and integer. all divi de instructions are iterative operations. they must be executed within a repeat loop, resulting in a total execution time of 19 instruction cycles. the divide operation can be interrupted during any of those 19 cycles witho ut loss of data. a 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a sing le cycle. the barrel shifter can be used by both mcu and dsp instructions. figure 3-1: dspic33fj32mc202/204 and ds pic33fj16mc304 cpu core block diagram instruction decode and control pch pcl program counter 16-bit alu 24 23 instruction reg pcu 16 x 16 w register array rom latch ea mux interrupt controller stack control logic loop control logic data latch address latch control signals to various blocks literal data 16 16 16 to peripheral modules data latch address latch 16 x ram y ram address generator units 16 y data bus x data bus dsp engine divide support 16 16 23 23 16 8 psv and table data access control block 16 16 16 16 program memory data latch address latch 16 16 16 16 16 16 24 ? 2007-2012 microchip technology inc. ds70283k-page 19 dspic33fj32mc202/204 and dspic33fj16mc304 figure 3-2: dspic33fj32mc202/204 and dspic33fj16mc304 programmer?s model pc22 pc0 7 0 d0 d15 program counter data table page address status register working registers dsp operand registers w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12/dsp offset w13/dsp write back w14/frame pointer w15/stack pointer dsp address registers ad39 ad0 ad31 dsp accumulators acca accb 7 0 program space visibi lity page address z 0 oa ob sa sb rcount 15 0 repeat loop counter dcount 15 0 do loop counter dostart 22 0 do loop start address ipl2 ipl1 splim stack pointer limit register ad15 srl push.s shadow do shadow oab sab 15 0 core configuration register legend corcon da dc ra n tblpag psvpag ipl0 ov w0/wreg srh do loop end address doend 22 c dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 20 ? 2007-2012 microchip technology inc. 3.4 cpu resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 3.4.1 key resources ? section 2. ?cpu? (ds70204) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 21 dspic33fj32mc202/204 and dspic33fj16mc304 3.5 cpu control registers register 3-1: sr: cpu status register r-0 r-0 r/c-0 r/c-0 r-0 r/c-0 r -0 r/w-0 oa ob sa (1) sb (1) oab sab da dc bit 15 bit 8 r/w-0 (3) r/w-0 (3) r/w-0 (3) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl<2:0> (2) ra n ov z c bit 7 bit 0 legend: c = clear only bit r = readable bit u = unimplemented bit, read as ?0? s = set only bit w = writable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 oa: accumulator a overflow status bit 1 = accumulator a overflowed 0 = accumulator a has not overflowed bit 14 ob: accumulator b overflow status bit 1 = accumulator b overflowed 0 = accumulator b has not overflowed bit 13 sa: accumulator a saturation ?sticky? status bit (1) 1 = accumulator a is saturated or has been saturated at some time 0 = accumulator a is not saturated bit 12 sb: accumulator b saturation ?sticky? status bit (1) 1 = accumulator b is saturated or has been saturated at some time 0 = accumulator b is not saturated bit 11 oab: oa || ob combined accumu lator overflow status bit 1 = accumulators a or b have overflowed 0 = neither accumulators a or b have overflowed bit 10 sab: sa || sb combined accumula tor ?sticky? status bit 1 = accumulators a or b are saturated or hav e been saturated at some time in the past 0 = neither accumulator a or b are saturated note: this bit may be read or cleared (not set). clearing this bit will clear sa and sb. bit 9 da: do loop active bit 1 = do loop in progress 0 = do loop not in progress bit 8 dc: mcu alu half carry/borrow bit 1 = a carry-out from the 4th low-order bit (for byte-s ized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = no carry-out from the 4th low-order bit (for by te-sized data) or 8th low- order bit (for word-sized data) of the result occurred note 1: this bit can be read or cleared (not set). 2: the ipl<2:0> bits are concatenated with the ipl<3> bi t (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when nstdis = 1 (intcon1<15>). dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 22 ? 2007-2012 microchip technology inc. bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (2) 111 = cpu interrupt priority level is 7 (15), user interrupts disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop in progress 0 = repeat loop not in progress bit 3 n: mcu alu negative bit 1 = result was negative 0 = result was non-negative (zero or positive) bit 2 ov: mcu alu overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of a magnitude that causes the sign bit to change state. 1 = overflow occurred for signed arit hmetic (in this arithmetic operation) 0 = no overflow occurred bit 1 z: mcu alu zero bit 1 = an operation that affects the z bit has set it at some time in the past 0 = the most recent operation that affects the z bit has cleared it (i.e., a non-zero result) bit 0 c: mcu alu carry/borrow bit 1 = a carry-out from the most sign ificant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred register 3-1: sr: cpu status register (continued) note 1: this bit can be read or cleared (not set). 2: the ipl<2:0> bits are concatenated with the ipl<3> bi t (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-only when nstdis = 1 (intcon1<15>). ? 2007-2012 microchip technology inc. ds70283k-page 23 dspic33fj32mc202/204 and dspic33fj16mc304 register 3-2: corcon: core control register u-0 u-0 u-0 r/w-0 r/w-0 r-0 r-0 r-0 ? ? ?usedt (1) dl<2:0> bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r/w-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 (2) psv rnd if bit 7 bit 0 legend: c = clear only bit r = readable bit w = writable bit -n = value at por ?1? = bit is set 0? = bit is cleared ?x = bit is unknown u = unimplemented bit, read as ?0? bit 15-13 unimplemented: read as ? 0 ? bit 12 us: dsp multiply unsigned/signed control bit 1 = dsp engine multiplies are unsigned 0 = dsp engine multiplies are signed bit 11 edt: early do loop termination control bit (1) 1 = terminate executing do loop at end of current loop iteration 0 = no effect bit 10-8 dl<2:0>: do loop nesting level status bits 111 = 7 do loops active ? ? ? 001 = 1 do loop active 000 = 0 do loops active bit 7 sata: acca saturation enable bit 1 = accumulator a saturation enabled 0 = accumulator a saturation disabled bit 6 satb: accb saturation enable bit 1 = accumulator b saturation enabled 0 = accumulator b saturation disabled bit 5 satdw: data space write from dsp engine saturation enable bit 1 = data space write saturation enabled 0 = data space write saturation disabled bit 4 accsat: accumulator saturation mode select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 ipl3: cpu interrupt priority level status bit 3 (2) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 2 psv: program space visibility in data space enable bit 1 = program space visible in data space 0 = program space not visible in data space bit 1 rnd: rounding mode select bit 1 = biased (conventional) rounding enabled 0 = unbiased (convergent) rounding enabled bit 0 if: integer or fractional multiplier mode select bit 1 = integer mode enabled for dsp multiply ops 0 = fractional mode enabled for dsp multiply ops note 1: this bit will always read as ? 0 ?. 2: the ipl3 bit is concatenated with t he ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 24 ? 2007-2012 microchip technology inc. 3.6 arithmetic logic unit (alu) the dspic33fj32mc202/204 and dspic33fj16mc304 alu is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. unless otherwise mentioned, arithmetic operations are 2?s complement in nature. depending on the operation, the alu can affect the values of the carry (c ), zero (z), negative (n), overflow (ov) and digit carry (dc) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bits, respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations, depending on the mode of t he instruction that is used. data for the alu operation can come from the w register array or data memory, depending on the addressing mode of the instruction. likewise, output data from the alu can be writte n to the w register array or a data memory location. refer to the ? 16-bit mcu and dsc programmer?s ref- erence manual? (ds70157) for information on the sr bits affected by each instruction. the dspic33fj32mc202/204 and dspic33fj16mc304 cpu incorporates hardware support for both multiplication and division. this includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. 3.6.1 multiplier using the high-speed 17-bit x 17-bit multiplier of the dsp engine, the alu supports unsigned, signed or mixed-sign operation in several mcu multiplication modes: ? 16-bit x 16-bit signed ? 16-bit x 16-bit unsigned ? 16-bit signed x 5-bit (literal) unsigned ? 16-bit unsigned x 16-bit unsigned ? 16-bit unsigned x 5-bit (literal) unsigned ? 16-bit unsigned x 16-bit signed ? 8-bit unsigned x 8-bit unsigned 3.6.2 divider the divide block supports 32- bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. 16-bit signed and unsigned div instructions can specify any w register for both the 16-bit divisor (wn) and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16- bit instructi ons take the same number of cycles to execute. 3.7 dsp engine the dsp engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two ta rget accumulators, round and saturation logic). the dspic33fj32mc202/204 and dspic33fj16mc304 is a single-cycle instruction flow architecture; therefore, concurrent operation of the dsp engine with mcu instruction flow is not possible. however, some mcu alu and dsp engine resources can be used concurrently by the same instruction (e.g., ed , edac ). the dsp engine can also perform inherent accumula- tor-to-accumulator operations that require no additional data. these instructions are add , sub and neg . the dsp engine has options selected through bits in the cpu core control register (corcon), as listed below: ? fractional or integer dsp multiply (if) ? signed or unsigned dsp multiply (us) ? conventional or convergent rounding (rnd) ? automatic saturation on/off for acca (sata) ? automatic saturation on/off for accb (satb) ? automatic saturation on/off for writes to data memory (satdw) ? accumulator saturation mode selection (accsat) a block diagram of the dsp engine is shown in figure 3-3 . table 3-1: dsp instructions summary instruction algebraic operation acc write back clr a = 0 yes ed a = (x - y) 2 no edac a = a + (x ? y) 2 no mac a = a + (x * y) yes mac a = a + x 2 no movsac no change in a yes mpy a = x ? y no mpy a = x 2 no mpy.n a = ? x ? y no msc a = a ? x ? y yes ? 2007-2012 microchip technology inc. ds70283k-page 25 dspic33fj32mc202/204 and dspic33fj16mc304 figure 3-3: dsp engine block diagram zero backfill sign-extend barrel shifter 40-bit accumulator a 40-bit accumulator b round logic x data bus to / f r o m w a r r a y adder saturate negate 32 32 33 16 16 16 16 40 40 40 40 s a t u r a t e y data bus 40 carry/borrow out carry/borrow in 16 40 multiplier/scaler 17-bit dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 26 ? 2007-2012 microchip technology inc. 3.7.1 multiplier the 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (q31) or 32-bit integer results. unsigned operands are zero-extended into the 17th bit of the multiplier input value. signed operands are sign-extended into the 17th bit of the multiplier input value. the ou tput of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. integer data is inherently represented as a signed 2?s complement value, where the most significant bit (msb) is defined as a sign bit. the range of an n-bit 2?s complement integer is -2 n-1 to 2 n-1 - 1. ? for a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7fff) including 0. ? for a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7fff ffff). when the multiplier is conf igured for fractional multipli- cation, the data is represented as a 2?s complement fraction, where the msb is defined as a sign bit and the radix point is implied to lie just after the sign bit (qx format). the range of an n-bit 2?s complement fraction with this implied radix point is -1.0 to (1 - 2 1-n ). for a 16-bit fraction, the q15 data range is -1.0 (0x8000) to 0.999969482 (0x7fff) including 0 and has a precision of 3.01518x10 -5 . in fractional mode, the 16 x 16 multi- ply operation generates a 1. 31 product that has a pre- cision of 4.65661 x 10 -10 . the same multiplier is used to support the mcu multi- ply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. the mul instruction can be directed to use byte or word-sized operands. byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the w array. 3.7.2 data accumulators and adder/subtracter the data accumulator consists of a 40-bit adder/subtracter with automatic sign extension logic. it can select one of two accumulators (a or b) as its pre-accumulation source and post-accumulation destination. for the add and lac instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. 3.7.2.1 adder/subtracter, overflow and saturation the adder/subtracter is a 40- bit adder with an optional zero input into one side, and either true or complement data into the other input. ? in the case of addition, the carry/b orrow input is active-high and the other input is true data (not complemented). ? in the case of subtraction, the carry/borrow input is active-low and the other input is complemented. the adder/subtracter generates overflow status bits, sa/sb and oa/ob, which are latched and reflected in the status register: ? overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. ? overflow into guard bits 32 through 39: this is a recoverable overflow. this bit is set whenever all the guard bits are not identical to each other. the adder has an additional saturation block that controls accumulator data saturation, if selected. it uses the result of the adder, the overflow status bits described previously and the sat ? 2007-2012 microchip technology inc. ds70283k-page 27 dspic33fj32mc202/204 and dspic33fj16mc304 the sa and sb bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. when set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit satu ration or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). when saturation is not enabled, sa and sb default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. if the covte bit in the intcon1 register is set, sa and sb bits will gener- ate an arithmetic warning trap when saturation is disabled. the overflow and saturation status bits can optionally be viewed in the status register (sr) as the logical or of oa and ob (in bit oab) and the logical or of sa and sb (in bit sab). programmers can check one bit in the status register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. th is is useful for complex number arithmetic, which typically uses both accumulators. the device supports three saturation and overflow modes: ? bit 39 overflow and saturation: when bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7fffffffff) or maximally negative 9.31 value (0x8000000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user application. this condition is referred to as ?super saturation? and pr ovides protection against erroneous data or unexpected algorithm problems (such as gain calculations). ? bit 31 overflow and saturation: when bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007fffffff) or maximally nega- tive 1.31 value (0x0080000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user application. when this saturation mode is in effect, the guard bits are not used, so the oa, ob or oab bits are never set. ? bit 39 catastrophic overflow: the bit 39 overflow status bit from the adder is used to set the sa or sb bit, which remains set until cleared by the user application. no saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. if the covte bit in the intcon1 register is set, a catastrophic overflow can initiate a trap exception. 3.7.3 accumulator ?write back? the mac class of instructions (with the exception of mpy , mpy.n , ed and edac ) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is no t targeted by the instruction into data space memory. the write is performed across the x bus into combined x and y address space. the following addressing modes are supported: ? w13, register direct: the rounded contents of the non-target accumulator are written into w13 as a 1.15 fraction. ? [w13] + = 2, register indirect with post-increment: the rounded contents of the non-target accumulator are written into the address pointed to by w13 as a 1.15 fraction. w13 is then incremented by 2 (for a word write). 3.7.3.1 round logic the round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). the round mode is determined by the state of the rnd bit in the corcon register. it generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. if rounding is not indicated by the instruction, a truncated 1. 15 data value is stored and the least significant word (lsw) is simply discarded. conventional rounding zero-extends bit 15 of the accumulator and adds it to the accxh word (bits 16 through 31 of the accumulator). ? if the accxl word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xffff (0x8000 included), accxh is incremented. ? if accxl is between 0x0000 and 0x7fff, accxh is left unchanged. a consequence of this al gorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when accxl equals 0x8000. in this case, the least significant bit (bit 16 of the accumulator) of accxh is examined: ? if it is ? 1 ?, accxh is incremented. ? if it is ? 0 ?, accxh is not modified. assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. the sac and sac.r instructions store either a truncated ( sac ), or rounded ( sac.r ) version of the contents of the target accumulator to data memory via the x bus, subject to data saturation (see section 3.7.3.2 ?data space write saturation? ). for the mac class of instructio ns, the accumulator write-back operation functi ons in the same manner, addressing combined mcu (x and y) data space though the x bus. for this class of instructions, the data is always subject to rounding. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 28 ? 2007-2012 microchip technology inc. 3.7.3.2 data space write saturation in addition to adder/subtracter saturation, writes to data space can also be saturat ed, but without affecting the contents of the source accumulator. the data space write saturation logic block accepts a 16-bit, 1.15 frac- tional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. these inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. if the satdw bit in the corcon register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: ? for input data greater than 0x007fff, data writ- ten to memory is forced to the maximum positive 1.15 value, 0x7fff. ? for input data less than 0xff8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. the most significant bit of t he source (bit 39) is used to determine the sign of the operand being tested. if the satdw bit in the corco n register is not set, the input data is always passed through unmodified under all conditions. 3.7.4 barrel shifter the barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. the source can be eith er of the two dsp accu- mulators or the x bus (to support multi-bit shifts of register or memory data). the shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. a positive value shifts the operand right. a negative value shifts the operand left. a value of ? 0 ? does not modify the operand. the barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for dsp shift operations and a 16-bit result for mcu shift operations. data from the x bus is pre- sented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. ? 2007-2012 microchip technology inc. ds70283k-page 29 dspic33fj32mc202/204 and dspic33fj16mc304 4.0 memory organization the dspic33fj32mc202/204 and dspic33fj16mc304 architecture features separate program and data memory spaces and buses. this architecture also allows the direct access of program memory from the data space during code execution. 4.1 program address space the program address memory space of the dspic33fj32mc202/204 and dspic33fj16mc304 devices is 4m instructions. the space is addressable by a 24-bit value derived either from the 23-bit program counter (pc) during program execution, or from table operation or data space remapping as described in section 4.8 ?interfacing program and data memory spaces? . user application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7fffff). the exception is the use of tblrd/tblwt operations, which use tblpag<7> to permit access to the configuration bits and device id sections of the configuration memory space. the memory maps for the dspic33fj32mc202/204 and dspic33fj16mc304 devices are shown in figure 4-1 . figure 4-1: program memory maps for ds pic33fj32mc202/204 and dspic33fj16mc304 devices note: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 4. ?program memory? (ds70202) of the ?dspic33f/pic24h family reference manual?, which is avail- able from the microchip web site ( www.microchip.com ). reset address 0x000000 0x0000fe 0x000002 0x000100 device configuration user program flash memory 0x005800 0x0057fe (11264 instructions) 0x800000 0xf80000 registers 0xf80017 0xf80018 devid (2) 0xfefffe 0xff0000 0xfffffe 0xf7fffe unimplemented (read ? 0 ?s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe 0x000104 alternate vector table reserved interrupt vector table dspic33fj32mc202/204 configuration memory space user memory space reset address 0x000000 0x0000fe 0x000002 0x000100 device configuration user program flash memory 0x002c00 0x002bfe (5632 instructions) 0x800000 0xf80000 registers 0xf80017 0xf80018 devid (2) 0xfefffe 0xff0000 0xfffffe 0xf7fffe unimplemented (read ? 0 ?s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe 0x000104 alternate vector table reserved interrupt vector table dspic33fj16mc304 configuration memory space user memory space dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 30 ? 2007-2012 microchip technology inc. 4.1.1 program memory organization the program memory space is organized in word-addressable blocks. al though it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address ( figure 4-2 ). program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. this arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. 4.1.2 interrupt and trap vectors all dspic33fj32mc202/ 204 and dspic33fj16mc304 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. a hardware reset vector is provided to redirect code execution from the default value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user a pplication at 0x000000, with the actual address for the start of code at 0x000002. dspic33fj32mc202/204 and dspic33fj16mc304 devices also have two interrupt vector tables, located from 0x000004 to 0x0000ff and 0x000100 to 0x0001ff. these vector tables allow each of the device interrupt sources to be handled by separate interrupt service routines (isrs). a more detailed discussion of the interrupt vector tables is provided in section 7.1 ?interrupt vector table? . figure 4-2: program memory organization 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) least significant word most significant word instruction width 0x000001 0x000003 0x000005 0x000007 msw address (lsw address) ? 2007-2012 microchip technology inc. ds70283k-page 31 dspic33fj32mc202/204 and dspic33fj16mc304 4.2 data address space the dspic33fj32mc202/204 and dspic33fj16mc304 cpu has a separate 16-bit-wide data memory space. the data space is accessed using separate address generation units (agus) for read and write operations. the data memory maps is shown in figure 4-3 . all effective addresses (eas) in the data memory space are 16 bits wide and point to bytes within the data space. this arrangement gives a data space address range of 64 kbytes or 32k words. the lower half of the data memory space (that is, when ea<15> = 0 ) is used for implemented memory addresses, while the upper half (ea<15> = 1 ) is reserved for the program space visibility area (see section 4.8.3 ?reading data from program memory using program space visibility? ). dspic33fj32mc202/204 and dspic33fj16mc304 devices implement up to 2 kbytes of data memory. should an ea point to a location outside of this area, an all-zero word or byte will be returned. 4.2.1 data space width the data memory space is organized in byte addressable, 16-bit wide blocks. data is aligned in data memory and registers as 16-bit words, but all data space eas resolve to bytes. the least significant bytes (lsbs) of each word have even addresses, while the most significant bytes (msbs) have odd addresses. 4.2.2 data memory organization and alignment to maintain backward compatibility with pic ? mcu devices and improve data space memory usage efficiency, the dspic33fj32mc202/204 and dspic33fj16mc304 instruction set supports both word and byte operations. as a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [ws++] will result in a value of ws + 1 for byte operations and ws + 2 for word operations. data byte reads will read the complete word that contains the byte, using the lsb of any ea to determine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. data byte writes only write to the corresponding side of the array or register that matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap is generated. if the e rror occurred on a read, the instruction underway is completed. if the error occurred on a write, the instruction is executed but the write does not occur. in either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the least significant byte. the most significant byte is not modified. a sign-extend instruction ( se ) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, user applications can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. 4.2.3 sfr space the first 2 kbytes of the near data space, from 0x0000 to 0x07ff, is primarily occupied by special function registers (sfrs). these are used by the dspic33fj32mc202/204 and dspic33fj16mc304 core and peripheral modules for controlling the operation of the device. sfrs are distributed amon g the modules that they control, and are generally grouped together by module. much of the sfr space contains unused addresses; these are read as ? 0 ?. 4.2.4 near data space the 8 kbyte area between 0x0000 and 0x1fff is referred to as the near data space. locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. additionally, the whole data space is addressable using mov instructions, which support memory direct addressing mode with a 16-bit address field, or by using indirect addressing mode using a working register as an address pointer. note: the actual set of peripheral features and interrupts varies by the device. refer to the corresponding device tables and pinout diagrams for device-specific information. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 32 ? 2007-2012 microchip technology inc. figure 4-3: data memory map for dspic3 3fj32mc202/204 and dspic33fj16mc304 devices with 2 kb ram 0x0000 0x07fe 0x0ffe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0xffff optionally mapped into program memory 0x0801 0x0800 0x1000 2 kbyte sfr space 2 kbyte sram space 0x8001 0x8000 sfr space x data ram (x) x data unimplemented (x) y data ram (y) 0x0bfe 0x0c00 0x0bff 0x0001 0x0fff 0x1001 0x1fff 0x1ffe 0x2001 0x2000 8 kbyte near data space ? 2007-2012 microchip technology inc. ds70283k-page 33 dspic33fj32mc202/204 and dspic33fj16mc304 4.2.5 x and y data spaces the core has two data spaces, x and y. these data spaces can be considered either separate (for some dsp instructions), or as one unified linear address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. this feature allows certain instructions to concurrently fetch two words from ram, thereby enabling efficient ex ecution of dsp algorithms such as finite impulse response (fir) filtering and fast fourier transform (fft). the x data space is used by all instructions and supports all addressing modes. x data space has separate read and write data buses. the x read data bus is the read data path for all instructions that view data space as combined x and y address space. it is also the x data prefetch pa th for the dual operand dsp instructions ( mac class). the y data space is used in concert with the x data space by the mac class of instructions ( clr , ed , edac , mac , movsac , mpy , mpy.n and msc ) to provide two concurrent data read paths. both the x and y data spaces support modulo addressing mode for all instructions, subject to addressing mode restrictions . bit-reversed addressing mode is only supported for writes to x data space. all data memory writes, including in dsp instructions, view data space as combined x and y address space. the boundary between the x and y data spaces is device-dependent and is not user-programmable. all effective addresses are 16 bits wide and point to bytes within the data space. therefore, the data space address range is 64 kbytes, or 32k words, though the implemented memory locations vary by device. 4.3 program memory resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 4.3.1 key resources ? section 4. ?program memory? (ds70202) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 34 ? 2007-2012 microchip technology inc. 4.4 special function register maps table 4-1: cpu core registers map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets wreg0 0000 working register 0 0000 wreg1 0002 working register 1 0000 wreg2 0004 working register 2 0000 wreg3 0006 working register 3 0000 wreg4 0008 working register 4 0000 wreg5 000a working register 5 0000 wreg6 000c working register 6 0000 wreg7 000e working register 7 0000 wreg8 0010 working register 8 0000 wreg9 0012 working register 9 0000 wreg10 0014 working register 10 0000 wreg11 0016 working register 11 0000 wreg12 0018 working register 12 0000 wreg13 001a working register 13 0000 wreg14 001c working register 14 0000 wreg15 001e working register 15 0800 splim 0020 stack pointer limit register xxxx accal 0022 accumulator a low word register 0000 accah 0024 accumulator a high word register 0000 accau 0026 accumulator a upper word register 0000 accbl 0028 accumulator b low word register 0000 accbh 002a accumulator b high word register 0000 accbu 002c accumulator b upper word register 0000 pcl 002e program counter low word register 0000 pch 0030 ? ? ? ? ? ? ? ? program counter high byte register 0000 tblpag 0032 ? ? ? ? ? ? ? ? table page address pointer register 0000 psvpag 0034 ? ? ? ? ? ? ? ? program memory visibility page address pointer register 0000 rcount 0036 repeat loop counter register xxxx dcount 0038 dcount<15:0> xxxx dostartl 003a dostartl<15:1> 0xxxx dostarth 003c ? ? ? ? ? ? ? ? ? ? dostarth<5:0> 00xx doendl 003e doendl<15:1> 0xxxx doendh 0040 ? ? ? ? ? ? ? ? ? ? doendh 00xx sr 0042 oa ob sa sb oab sab da dc ipl2 ipl1 ipl0 ra n ov z c 0000 corcon 0044 ? ? ? us edt dl<2:0> sata satb satdw accsat ipl3 psv rnd if 0020 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. ? 2007-2012 microchip technology inc. ds70283k-page 35 dspic33fj32mc202/204 and dspic33fj16mc304 modcon 0046 xmoden ymoden ? ? bwm<3:0> ywm<3:0> xwm<3:0> 0000 xmodsrt 0048 xs<15:1> 0xxxx xmodend 004a xe<15:1> 1xxxx ymodsrt 004c ys<15:1> 0xxxx ymodend 004e ye<15:1> 1xxxx xbrev 0050 bren xb<14:0> xxxx disicnt 0052 ? ? disable interrupts counter register xxxx table 4-1: cpu core registers map (continued) sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-2: change notification re gister map for dspic33fj32mc202 sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie ? ? ? cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 ? cn30ie cn29ie ? cn27ie ? ? cn24ie cn23ie cn22ie cn21ie ? ? ? ? cn16ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue ? ? ? cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a ? cn30pue cn29pue ? cn27pue ? ? cn24pue cn23pue cn22pue cn21pue ? ? ? ? cn16pue 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-3: change notification register map for dspic33fj32mc204 and dspic33fj16mc304 sfr name sfr addr bit 15bit 14bit 13bit 12bit 11bit 10bit 9bit 8bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 all resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie cn10ie cn9 ie cn8ie cn7ie cn6ie cn5ie cn4 ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 ? cn30ie cn29ie cn28ie cn27ie cn26ie cn25ie cn24ie cn2 3ie cn22ie cn21ie cn20ie cn19ie cn18ie cn17ie cn16ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue cn10pue cn9pue cn8pue cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a ? cn30pue cn29pue cn28pue cn27pue cn26pue cn25pue cn24pue cn23pue cn22pue cn21pue cn20pue cn19pue cn18pue cn17pue cn16pue 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 36 ? 2007-2012 microchip technology inc. table 4-4: interrupt controller register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets intcon1 0080 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sftacerr div0err ? matherr addrerr stkerr oscfail ? 0000 intcon2 0082 altivt disi ? ? ? ? ? ? ? ? ? ? ? int2ep int1ep int0ep 0000 ifs0 0084 ? ? ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if ? t1if oc1if ic1if int0if 0000 ifs1 0086 ? ?int2if ? ? ? ? ?ic8ific7if ?int1ifcnif ?mi2c1ifsi2c1if 0000 ifs3 008a flta1if ? ? ? ? qeiif pwm1if ? ? ? ? ? ? ? ? ? 0000 ifs4 008c ? ? ? ? ? flta2if pwm2if ? ? ? ? ? ? ?u1eif ? 0000 iec0 0094 ? ? ad1ie u1txie u1rxie spi1ie spi1eie t3ie t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie 0000 iec1 0096 ? ?int2ie ? ? ? ? ?ic8ieic7ie ? int1ie cnie ? mi2c1ie si2c1ie 0000 iec3 009a flta1ie ? ? ? ?qeiiepwm1ie ? ? ? ? ? ? ? ? ? 0000 iec4 009c ? ? ? ? ? flta2ie pwm2ie ? ? ? ? ? ? ?u1eie ? 0000 ipc0 00a4 ? t1ip<2:0> ? oc1ip<2:0> ? ic1ip<2:0> ? int0ip<2:0> 4444 ipc1 00a6 ? t2ip<2:0> ? oc2ip<2:0> ? ic2ip<2:0> ? ? ? ? 4440 ipc2 00a8 ? u1rxip<2:0> ? spi1ip<2:0> ? spi1eip<2:0> ? t3ip<2:0> 4444 ipc3 00aa ? ? ? ? ? ? ? ? ? ad1ip<2:0> ? u1txip<2:0> 0044 ipc4 00ac ? cnip<2:0> ? ? ? ? ? mi2c1ip<2:0> ? si2c1ip<2:0> 4044 ipc5 00ae ?ic8ip<2:0> ?ic7ip<2:0> ? ? ? ? ? int1ip<2:0> 4404 ipc7 00b2 ? ? ? ? ? ? ? ? ? int2ip<2:0> ? ? ? ? 0040 ipc14 00c0 ? ? ? ? ?qeiip<2:0> ? pwm1ip<2:0> ? ? ? ? 0440 ipc15 00c2 ?flta1ip<2:0> ? ? ? ? ? ? ? ? ? ? ? ? 4000 ipc16 00c4 ? ? ? ? ? ? ? ? ? u1eip<2:0> ? ? ? ? 0040 ipc18 00c8 ? ? ? ? ?flta2ip<2:0> ? pwm2ip<2:0> ? ? ? ? 0440 inttreg 00e0 ? ? ? ?ilr<3:0> ? vecnum<6:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. ? 2007-2012 microchip technology inc. ds70283k-page 37 dspic33fj32mc202/204 and dspic33fj16mc304 table 4-5: timer register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register 0000 pr1 0102 period register 1 ffff t1con 0104 ton ? tsidl ? ? ? ? ? ? tgate tckps<1:0> ? tsync tcs ? 0000 tmr2 0106 timer2 register 0000 tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) xxxx tmr3 010a timer3 register 0000 pr2 010c period register 2 ffff pr3 010e period register 3 ffff t2con 0110 ton ? tsidl ? ? ? ? ? ? tgate tckps<1:0> t32 ? tcs ? 0000 t3con 0112 ton ? tsidl ? ? ? ? ? ? tgate tckps<1:0> ? ? tcs ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-6: input capture register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1buf 0140 input 1 capture register xxxx ic1con 0142 ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 ic2buf 0144 input 2 capture register xxxx ic2con 0146 ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 ic7buf 0158 input 7 capture register xxxx ic7con 015a ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 ic8buf 015c input 8 capture register xxxx ic8con 015e ? ? icsidl ? ? ? ? ? ictmr ici<1:0> icov icbne icm<2:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-7: output compare register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1rs 0180 output compare 1 secondary register xxxx oc1r 0182 output compare 1 register xxxx oc1con 0184 ? ? ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 oc2rs 0186 output compare 2 secondary register xxxx oc2r 0188 output compare 2 register xxxx oc2con 018a ? ? ocsidl ? ? ? ? ? ? ? ? ocflt octsel ocm<2:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 38 ? 2007-2012 microchip technology inc. table 4-8: 6-output pwm1 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state p1tcon 01c0 pten ?ptsidl ? ? ? ? ? ptops<3:0> ptckps<1:0> ptmod<1:0> 0000 0000 0000 0000 p1tmr 01c2 ptdir pwm timer count value register 0000 0000 0000 0000 p1tper 01c4 ? pwm time base period register 0000 0000 0000 0000 p1secmp 01c6 sevtdir pwm special event compare register 0000 0000 0000 0000 pwm1con1 01c8 ? ? ? ? ?pmod3pmod2pmod1 ? pen3h pen2h pen1h ? pen3l pen2l pen1l 0000 0000 1111 1111 pwm1con2 01ca ? ? ? ? sevops<3:0> ? ? ? ? ? iue osync udis 0000 0000 0000 0000 p1dtcon1 01cc dtbps<1:0> dtb<5:0> dtaps<1:0> dta<5:0> 0000 0000 0000 0000 p1dtcon2 01ce ? ? ? ? ? ? ? ? ? ? dts3a dts3i dts2a dts2i dts1a dts1i 0000 0000 0000 0000 p1fltacon 01d0 ? ? faov3h faov3l faov2h faov2l faov1h faov1l fltam ? ? ? ? faen3 faen2 faen1 0000 0000 0000 0000 p1ovdcon 01d4 ? ? povd3h povd3l povd2h povd2l povd1h povd1l ? ? pout3h pout3l pout2h pout2l pout1h pout1l 1111 1111 0000 0000 p1dc1 01d6 pwm duty cycle #1 register 0000 0000 0000 0000 p1dc2 01d8 pwm duty cycle #2 register 0000 0000 0000 0000 p1dc3 01da pwm duty cycle #3 register 0000 0000 0000 0000 legend: u = uninitialized bit, ? = unimplemented, read as ? 0 ? table 4-9: 2-output pwm2 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state p2tcon 05c0 pten ?ptsidl ? ? ? ? ? ptops<3:0> ptckps<1:0> ptmod<1:0> 0000 0000 0000 0000 p2tmr 05c2 ptdir pwm timer count value register 0000 0000 0000 0000 p2tper 05c4 ? pwm time base period register 0000 0000 0000 0000 p2secmp 05c6 sevtdir pwm special event compare register 0000 0000 0000 0000 pwm2con1 05c8 ? ? ? ? ? ? ?pmod1 ? ? ?pen1h ? ? ? pen1l 0000 0000 1111 1111 pwm2con2 05ca ? ? ? ? sevops<3:0> ? ? ? ? ? iue osync udis 0000 0000 0000 0000 p2dtcon1 05cc dtbps<1:0> dtb<5:0> dtaps<1:0> dta<5:0> 0000 0000 0000 0000 p2dtcon2 05ce ? ? ? ? ? ? ? ? ? ? ? ? ? ?dts1adts1i 0000 0000 0000 0000 p2fltacon 05d0 ? ? ? ? ? ? faov1h faov1l fltam ? ? ? ? ? ?faen1 0000 0000 0000 0000 p2ovdcon 05d4 ? ? ? ? ? ? povd1h povd1l ? ? ? ? ? ? pout1h pout1l 1111 1111 0000 0000 p2dc1 05d6 pwm duty cycle #1 register 0000 0000 0000 0000 legend: u = uninitialized bit, ? = unimplemented, read as ? 0 ? ? 2007-2012 microchip technology inc. ds70283k-page 39 dspic33fj32mc202/204 and dspic33fj16mc304 table 4-10: qei1 register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state qei1con 01e0 cnterr ? qeisidl index updn qeim<2:0> swpab pcdout tqgate tqckps<1:0> posres tqcs updn_src 0000 0000 0000 0000 dflt1con 01e2 ? ? ? ? ? imv<1:0> ceid qeout qeck<2:0> ? ? ? ? 0000 0000 0000 0000 pos1cnt 01e4 position counter<15:0> 0000 0000 0000 0000 max1cnt 01e6 maximum count<15:0> 1111 1111 1111 1111 legend: u = uninitialized bit, ? = unimplemented, read as ? 0 ? table 4-11: i2c1 register map sfr name sfr addr bit 15bit 14bit 13bit 12bit 11bit 10bit 9bit 8bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 all resets i2c1rcv 0200 ? ? ? ? ? ? ? ? receive register 0000 i2c1trn 0202 ? ? ? ? ? ? ? ? transmit register 00ff i2c1brg 0204 ? ? ? ? ? ? ? baud rate generator register 0000 i2c1con 0206 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c1stat 0208 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 i2c1add 020a ? ? ? ? ? ? address register 0000 i2c1msk 020c ? ? ? ? ? ? address mask register 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-12: uart1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud urxinv brgh pdsel<1:0> stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 u1txreg 0224 ? ? ? ? ? ? ? uart transmit register xxxx u1rxreg 0226 ? ? ? ? ? ? ? uart receive register 0000 u1brg 0228 baud rate generator prescaler 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-13: spi1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets spi1stat 0240 spien ? spisidl ? ? ? ? ? ? spirov ? ? ? ? spitbf spirbf 0000 spi1con1 0242 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre<2:0> ppre<1:0> 0000 spi1con2 0244 frmen spifsd frmpol ? ? ? ? ? ? ? ? ? ? ? frmdly ? 0000 spi1buf 0248 spi1 transmit and receive buffer register 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 40 ? 2007-2012 microchip technology inc. table 4-14: adc1 register map for dspic33fj32mc202 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all reset s adc1buf0 0300 adc data buffer 0 xxxx adc1buf1 0302 adc data buffer 1 xxxx adc1buf2 0304 adc data buffer 2 xxxx adc1buf3 0306 adc data buffer 3 xxxx adc1buf4 0308 adc data buffer 4 xxxx adc1buf5 030a adc data buffer 5 xxxx adc1buf6 030c adc data buffer 6 xxxx adc1buf7 030e adc data buffer 7 xxxx adc1buf8 0310 adc data buffer 8 xxxx adc1buf9 0312 adc data buffer 9 xxxx adc1bufa 0314 adc data buffer 10 xxxx adc1bufb 0316 adc data buffer 11 xxxx adc1bufc 0318 adc data buffer 12 xxxx adc1bufd 031a adc data buffer 13 xxxx adc1bufe 031c adc data buffer 14 xxxx adc1buff 031e adc data buffer 15 xxxx ad1con1 0320 adon ?adsidl ? ? ad12b form<1:0> ssrc<2:0> ? simsam asam samp done 0000 ad1con2 0322 vcfg<2:0> ? ? cscna chps<1:0> bufs ? smpi<3:0> bufm alts 0000 ad1con3 0324 adrc ? ? samc<4:0> adcs<7:0> 0000 ad1chs123 0326 ? ? ? ? ? ch123nb<1:0> ch123sb ? ? ? ? ? ch123na<1:0> ch123sa 0000 ad1chs0 0328 ch0nb ? ? ch0sb<4:0> ch0na ? ? ch0sa<4:0> 0000 ad1pcfgl 032c ? ? ? ? ? ? ? ? ? ? pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 ad1cssl 0330 ? ? ? ? ? ? ? ? ? ? css5 css4 css3 css2 css1 css0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. ? 2007-2012 microchip technology inc. ds70283k-page 41 dspic33fj32mc202/204 and dspic33fj16mc304 table 4-15: adc1 register map for ds pic33fj32mc204 and dspic33fj16mc304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc data buffer 0 xxxx adc1buf1 0302 adc data buffer 1 xxxx adc1buf2 0304 adc data buffer 2 xxxx adc1buf3 0306 adc data buffer 3 xxxx adc1buf4 0308 adc data buffer 4 xxxx adc1buf5 030a adc data buffer 5 xxxx adc1buf6 030c adc data buffer 6 xxxx adc1buf7 030e adc data buffer 7 xxxx adc1buf8 0310 adc data buffer 8 xxxx adc1buf9 0312 adc data buffer 9 xxxx adc1bufa 0314 adc data buffer 10 xxxx adc1bufb 0316 adc data buffer 11 xxxx adc1bufc 0318 adc data buffer 12 xxxx adc1bufd 031a adc data buffer 13 xxxx adc1bufe 031c adc data buffer 14 xxxx adc1buff 031e adc data buffer 15 xxxx ad1con1 0320 adon ?adsidl ? ? ad12b form<1:0> ssrc<2:0> ? simsam asam samp done 0000 ad1con2 0322 vcfg<2:0> ? ? cscna chps<1:0> bufs ? smpi<3:0> bufm alts 0000 ad1con3 0324 adrc ? ? samc<4:0> adcs<7:0> 0000 ad1chs123 0326 ? ? ? ? ? ch123nb<1:0> ch123sb ? ? ? ? ? ch123na<1:0> ch123sa 0000 ad1chs0 0328 ch0nb ? ? ch0sb<4:0> ch0na ? ? ch0sa<4:0> 0000 ad1pcfgl 032c ? ? ? ? ? ? ? pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 ad1cssl 0330 ? ? ? ? ? ? ? css8 css7 css6 css5 css4 css3 css2 css1 css0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 42 ? 2007-2012 microchip technology inc. table 4-16: peripheral pin select input register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 0680 ? ? ? int1r<4:0> ? ? ? ? ? ? ? ? 1f00 rpinr1 0682 ? ? ? ? ? ? ? ? ? ? ?int2r<4:0> 001f rpinr3 0686 ? ? ?t3ckr<4:0> ? ? ?t2ckr<4:0> 1f1f rpinr7 068e ? ? ? ic2r<4:0> ? ? ? ic1r<4:0> 1f1f rpinr10 0694 ? ? ? ic8r<4:0> ? ? ? ic7r<4:0> 1f1f rpinr11 0696 ? ? ? ? ? ? ? ? ? ? ?ocfar<4:0> 001f rpinr12 0698 ? ? ? ? ? ? ? ? ? ? ?flta1r<4:0> 001f rpinr13 069a ? ? ? ? ? ? ? ? ? ? ?flta2r<4:0> 001f rpinr14 069c ? ? ? qeb1r<4:0> ? ? ?qea1r<4:0> 1f1f rpinr15 069e ? ? ? ? ? ? ? ? ? ? ? indx1r<4:0> 001f rpinr18 06a4 ? ? ? u1ctsr<4:0> ? ? ?u1rxr<4:0> 1f1f rpinr20 06a8 ? ? ?sck1r<4:0> ? ? ?sdi1r<4:0> 1f1f rpinr21 06aa ? ? ? ? ? ? ? ? ? ? ? ss1r<4:0> 001f legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-17: peripheral pin select output register map fo r dspic33fj32mc202 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 ? ? ? rp1r<4:0> ? ? ? rp0r<4:0> 0000 rpor1 06c2 ? ? ? rp3r<4:0> ? ? ? rp2r<4:0> 0000 rpor2 06c4 ? ? ? rp5r<4:0> ? ? ? rp4r<4:0> 0000 rpor3 06c6 ? ? ? rp7r<4:0> ? ? ? rp6r<4:0> 0000 rpor4 06c8 ? ? ? rp9r<4:0> ? ? ? rp8r<4:0> 0000 rpor5 06ca ? ? ?rp11r<4:0> ? ? ? rp10r<4:0> 0000 rpor6 06cc ? ? ?rp13r<4:0> ? ? ? rp12r<4:0> 0000 rpor7 06ce ? ? ?rp15r<4:0> ? ? ? rp14r<4:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. ? 2007-2012 microchip technology inc. ds70283k-page 43 dspic33fj32mc202/204 and dspic33fj16mc304 table 4-18: peripheral pin select output register map for dspic 33fj32mc204 and dspic33fj16mc304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 ? ? ? rp1r<4:0> ? ? ? rp0r<4:0> 0000 rpor1 06c2 ? ? ? rp3r<4:0> ? ? ?rp2r<4:0> 0000 rpor2 06c4 ? ? ? rp5r<4:0> ? ? ?rp4r<4:0> 0000 rpor3 06c6 ? ? ? rp7r<4:0> ? ? ?rp6r<4:0> 0000 rpor4 06c8 ? ? ? rp9r<4:0> ? ? ?rp8r<4:0> 0000 rpor5 06ca ? ? ?rp11r<4:0> ? ? ? rp10r<4:0> 0000 rpor6 06cc ? ? ?rp13r<4:0> ? ? ? rp12r<4:0> 0000 rpor7 06ce ? ? ?rp15r<4:0> ? ? ? rp14r<4:0> 0000 rpor8 06d0 ? ? ?rp17r<4:0> ? ? ? rp16r<4:0> 0000 rpor9 06d2 ? ? ?rp19r<4:0> ? ? ? rp18r<4:0> 0000 rpor10 06d4 ? ? ?rp21r<4:0> ? ? ? rp20r<4:0> 0000 rpor11 06d6 ? ? ?rp23r<4:0> ? ? ? rp22r<4:0> 0000 rpor12 06d8 ? ? ?rp25r<4:0> ? ? ? rp24r<4:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-19: porta register map for dspic33fj32mc202 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 ? ? ? ? ? ? ? ? ? ? ? trisa4 trisa3 trisa2 trisa1 trisa0 001f porta 02c2 ? ? ? ? ? ? ? ? ? ? ? ra4 ra3 ra2 ra1 ra0 xxxx lata 02c4 ? ? ? ? ? ? ? ? ? ? ? lata4 lata3 lata2 lata1 lata0 xxxx odca 02c6 ? ? ? ? ? ? ? ? ? ? ? odca4 odca3 odca2 odca1 odca0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-20: porta register map for dspic33fj32mc204 and dspic33fj16mc304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 ? ? ? ? ? trisa10 trisa9 trisa8 trisa7 ? ? trisa4 trisa3 trisa2 trisa1 trisa0 079f porta 02c2 ? ? ? ? ? ra10 ra9 ra8 ra7 ? ? ra4 ra3 ra2 ra1 ra0 xxxx lata 02c4 ? ? ? ? ? lat10 lat8 lat8 lat7 ? ? lata4 lata3 lata2 lata1 lata0 xxxx odca 02c6 ? ? ? ? ? odca10 odca9 odca8 odca7 ? ? odca4 odca3 odca2 odca1 odca0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 44 ? 2007-2012 microchip technology inc. table 4-21: portb register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb6 trisb5 trisb1 trisb0 ffff portb 02ca rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb6 rb5 rb1 rb0 xxxx latb 02cc latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb6 latb5 latb1 latb0 xxxx odcb 02ce odcb15 odcb14 odcb13 odcb12 odcb11 odcb10 odcb9 odcb8 odcb7 odcb6 odcb5 odcb4 odcb6 odcb5 odcb1 odcb0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal for 100-pin devices. table 4-22: portc register map for dspic33fj32mc204 and dspic33fj16mc304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 02d0 ? ? ? ? ? ? trisc9 trisc8 trisc7 trisc6 trisc5 trisc4 trisc6 trisc5 trisc1 trisc0 03ff portc 02d2 ? ? ? ? ? ? rc9 rc8 rc7 rc6 rc5 rc4 rc6 rc5 rc1 rc0 xxxx latc 02d4 ? ? ? ? ? ? latc9 latc8 latc7 latc6 latc5 latc4 latc6 latc5 latc1 latc0 xxxx odcc 02d6 ? ? ? ? ? ? odcc9 odcc8 odcc7 odcc6 odcc5 odcc4 odcc6 odcc5 odcc1 odcc0 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-23: system control register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rcon 0740 trapr iopuwr ? ? ? ? cm vregs extr swr swdten wdto sleep idle bor por xxxx (1) osccon 0742 ?cosc<2:0> ? nosc<2:0> clklock iolock lock ?cf ? lposcen oswen 0300 (2) clkdiv 0744 roi doze<2:0> do zen frcdiv<2:0> pllpost<1:0> ? pllpre<4:0> 3040 pllfbd 0746 ? ? ? ? ? ? ? plldiv<8:0> 0030 osctun 0748 ? ? ? ? ? ? ? ? ? ?tun<5:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: rcon register reset values dependent on type of reset. 2: osccon register reset values dependent on the fosc configuration bits and by type of reset. ? 2007-2012 microchip technology inc. ds70283k-page 45 dspic33fj32mc202/204 and dspic33fj16mc304 table 4-24: nvm register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr ? ? ? ? ? ? erase ? ?nvmop<3:0> 0000 (1) nvmkey 0766 ? ? ? ? ? ? ? ? nvmkey<7:0> 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: reset value shown is for por only. value on other reset states is dependent on the state of memory write or erase operations at the time of reset. table 4-25: pmd register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 ? ? t3md t2md t1md qeimd pwm1md ? i2c1md ? u1md ? spi1md ? ? ad1md 0000 pmd2 0772 ic8md ic7md ? ? ? ?ic2mdic1md ? ? ? ? ? ?oc2mdoc1md 0000 pmd3 0774 ? ? ? ? ? ? ? ? ? ? ?pwm2md ? ? ? ? 0000 legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 46 ? 2007-2012 microchip technology inc. 4.4.1 software stack in addition to its use as a working register, the w15 register in the dspi c33fj32mc202/204 and dspic33fj16mc304 devices is also used as a software stack pointer. the stack pointer always points to the first available free word and grows from lower to higher addresses. it predecrements for stack pops and post-increments for stack pushes, as shown in figure 4-4 . for a pc push during any call instruction, the msb of t he pc is zero-extended before the push, ensuring that the msb is always clear. the stack pointer limit r egister (splim) associated with the stack pointer sets an upper address boundary for the stack. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to ? 0 ? because all stack operations must be word-aligned. whenever an ea is generated using w15 as a source or destination pointer, the resulting address is compared with the value in splim. if the contents of the stack pointer (w15) and the splim register are equal and a push operation is performed, a stack error trap will not occur. the stack error trap will occur on a subsequent push operation. fo r example, to cause a stack error trap when the stack grows beyond address 0x1000 in ram, initialize the splim with the value 0x0ffe. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be less than 0x0800. this prevents the stack from interfering with the special function register (sfr) space. a write to the splim register should not be immediately followed by an indirect read operation using w15. figure 4-4: call stack frame 4.4.2 data ram protection feature the dspic33f product family supports data ram protection features that enable segments of ram to be protected when used in conjunction with boot and secure code segment security. bsram (secure ram segment for bs) is accessible only from the boot segment flash code when enabled. ssram (secure ram segment for ram) is accessible only from the secure segment flash code when enabled. see table 4-1 for an overview of the bsram and ssram sfrs. 4.5 instruction addressing modes the addressing modes shown in table 4-26 form the basis of the addressing modes optimized to support the specific features of i ndividual instructions. the addressing modes provided in the mac class of instructions differ from th ose in the other instruction types. 4.5.1 file register instructions most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). most file register instructions employ a working register, w0, which is denoted as wreg in these instructions. the destination is typically either the same file register or wreg (with the exception of the mul instruction), which writes the result to a register or register pair. the mov instruction allows additional flexibility and can access the entire data space. 4.5.2 mcu instructions the three-operand mcu instru ctions are of the form: operand 3 = operand 1 ? 2007-2012 microchip technology inc. ds70283k-page 47 dspic33fj32mc202/204 and dspic33fj16mc304 table 4-26: fundamental addressing modes supported 4.5.3 move and accumulator instructions move instructions and the dsp accumulator class of instructions provide a great er degree of addressing flexibility than other instructions. in addition to the addressing modes supported by most mcu instructions, move and accu mulator instructions also support register indire ct with register offset addressing mode, also referred to as register indexed mode. in summary, the following addressing modes are supported by move and accumulator instructions: ? register direct ? register indirect ? register indirect post-modified ? register indirect pre-modified ? register indirect with register offset (indexed) ? register indirect with literal offset ? 8-bit literal ? 16-bit literal 4.5.4 mac instructions the dual source operand dsp instructions ( clr , ed , edac , mac , mpy , mpy.n , movsac and msc ), also referred to as mac instructions, use a simp lified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. the two-source operand pref etch registers must be members of the set {w8, w9, w10, w11}. for data reads, w8 and w9 are always directed to the x ragu, and w10 and w11 are always directed to the y agu. the effective addresses generated (before and after modification) must, therefore, be valid addresses within x data space for w8 and w9 and y data space for w10 and w11. in summary, the following addressing modes are supported by the mac class of instructions: ? register indirect ? register indirect post-modified by 2 ? register indirect post-modified by 4 ? register indirect post-modified by 6 ? register indirect with register offset (indexed) 4.5.5 other instructions besides the addressing modes outlined previously, some instructions use literal cons tants of various sizes. for example, bra (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as add acc , the source of an operand or result is implied by the opcode itself. certain operations, such as nop , do not have any operands. addressing mode description file register direct the address of the file register is specified explicitly. register direct the contents of a register are accessed directly. register indirect the contents of wn forms the effective address (ea). register indirect post-modified the contents of wn forms the ea. wn is post-modified (incremented or decremented) by a constant value. register indirect pre-modified wn is pre-modified (inc remented or decremented) by a signed constant value to form the ea. register indirect with register offset (register indexed) the sum of wn and wb forms the ea. register indirect with literal offset the sum of wn and a literal forms the ea. note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and destination ea. however, the 4-bit wb (register offset) field is shared by both source and destination (but typically only used by one). note: not all instructions support all the addressing modes given above. individual instructions may support different subsets of these addressing modes. note: register indirect with register offset addressing mode is available only for w9 (in x space) and w11 (in y space). dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 48 ? 2007-2012 microchip technology inc. 4.6 modulo addressing modulo addressing mode is a method of providing an automated means to support circular data buffers using hardware. the objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many dsp algorithms. modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). one circ ular buffer can be supported in each of the x (which also provides the pointers into program space) and y data spaces. modulo addressing can operate on any w register pointer. however, it is not advisable to use w14 or w15 for modulo addressing since these two registers ar e used as the stack frame pointer and stack pointer, respectively. in general, any particular circular buffer can be configured to operate in only one direction as there are certain restrictions on the bu ffer start address (for incre- menting buffers), or end address (for decrementing buffers), based upon the direction of the buffer. the only exception to the usage restrictions is for buffers that have a power-of-two length. as these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performe d on both the lower and upper address boundaries). 4.6.1 start and end address the modulo addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit modulo buffer address registers: xmodsrt, xmodend, ymodsrt and ymodend (see ta b l e 4 - 1 ). the length of a circular buffer is not directly specified. it is determined by the difference between the corresponding start and end addresses. the maximum possible length of the circular buffer is 32k words (64 kbytes). 4.6.2 w address register selection the modulo and bit-reversed addressing control register, modcon<15:0>, contains enable flags as well as a w register field to sp ecify the w address registers. the xwm and ywm fields select the registers that will operate with modulo addressing: ?if xwm = 15 , x ragu and x wagu modulo addressing is disabled. ?if ywm = 15 , y agu modulo addressing is disabled. the x address space pointer w register (xwm), to which modulo addressing is to be applied, is stored in modcon<3:0> (see table 4-1 ). modulo addressing is enabled for x data space when xwm is set to any value other than ? 15 ? and the xmoden bit is set at modcon<15>. the y address space pointer w register (ywm) to which modulo addressing is to be applied is stored in modcon<7:4>. modulo addressing is enabled for y data space when ywm is set to any value other than ? 15 ? and the ymoden bit is set at modcon<14>. figure 4-5: modulo addr essing operation example note: y space modulo addressing ea calculations assume word-sized data (lsb of every ea is always clear). 0x1100 0x1163 start addr = 0x1100 end addr = 0x1163 length = 0x0032 words byte address mov #0x1100, w0 mov w0, xmodsrt ;set modulo start address mov #0x1163, w0 mov w0, modend ;set modulo end address mov #0x8001, w0 mov w0, modcon ;enable w1, x agu for modulo mov #0x0000, w0 ;w0 holds buffer fill value mov #0x1110, w1 ;point w1 to buffer do again, #0x31 ;fill the 50 buffer locations mov w0, [w1++] ;fill the next location again: inc w0, w0 ;increment the fill value ? 2007-2012 microchip technology inc. ds70283k-page 49 dspic33fj32mc202/204 and dspic33fj16mc304 4.6.3 modulo addressing applicability modulo addressing can be applied to the effective address (ea) calculation associated with any w register. address boundaries check for addresses equal to: ? the upper boundary addresses for incrementing buffers ? the lower boundary addresses for decrementing buffers it is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). address changes can, th erefore, jump beyond boundaries and still be adjusted correctly. 4.7 bit-reversed addressing bit-reversed addressing mode is intended to simplify data re-ordering for radix-2 fft algorithms. it is supported by the x agu for data writes only. the modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. the address source and destination are kept in normal order. thus, the only operand requiring reversal is the modifier. 4.7.1 bit-reversed addressing implementation bit-reversed addressing mode is enabled in any of these situations: ? bwm bits (w register selection) in the modcon register are any value other than ? 15 ? (the stack cannot be accessed using bit-reversed addressing) ? the bren bit is set in the xbrev register ? the addressing mode used is register indirect with pre-increment or post-increment if the length of a bit-reversed buffer is m = 2 n bytes, the last ?n? bits of the data buffer start address must be zeros. xb<14:0> is the bit-reversed address modifier, or ?pivot point?, which is typically a constant. in the case of an fft computation, its value is equal to half of the fft data buffer size. when enabled, bit-reversed addressing is executed only for register indire ct with pre-increment or post-increment addressing and word-sized data writes. it will not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. when bit-reversed addressing is active, the w address pointer is always added to the address modifier (xb), and the offset associated with the register indirect addressing mode is ignored. in addition, as word-sized data is a requirement, the lsb of the ea is ignored (and always clear). if bit-reversed addressing has already been enabled by setting the bren bit (xbrev<15>), a write to the xbrev register should not be immediately followed by an indirect read operation using the w register that has been designated as the bit-reversed pointer. note: the modulo corrected effective address is written back to the register only when pre-modify or post-modify addressing mode is used to compute the effective address. when an address offset (such as [w7 + w2]) is used, modulo address correction is performed but the contents of the register remain unchanged. note: all bit-reversed ea calculations assume word-sized data (lsb of every ea is always clear). the xb value is scaled accordingly to generate compatible (byte) addresses. note: modulo addressing and bit-reversed addressing should not be enabled together. if an application attempts to do so, bit-reversed addressing will assume priority when active for the x wagu and x wagu, modulo addressing will be disabled. however, modulo addressing will continue to function in the x ragu. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 50 ? 2007-2012 microchip technology inc. figure 4-6: bit-reversed address example table 4-27: bit-reversed address sequence (16-entry) b3 b2 b1 0 b2 b3 b4 0 bit locations swapped left-to-right around center of binary value bit-reversed address xb = 0x0008 for a 16-word bit-reversed buffer b7 b6 b5 b1 b7 b6 b5 b4 b11 b10 b9 b8 b11 b10 b9 b8 b15 b14 b13 b12 b15 b14 b13 b12 sequential address pivot point normal address bit-reversed address a3 a2 a1 a0 decimal a3 a2 a1 a0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15 ? 2007-2012 microchip technology inc. ds70283k-page 51 dspic33fj32mc202/204 and dspic33fj16mc304 4.8 interfacing program and data memory spaces the dspic33fj32mc202/204 and dspic33fj16mc304 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. the architecture is also a modified harvard scheme, meaning that data can also be present in the program space. to use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. aside from normal execution, the dspic33fj32mc202/204 and dspic33fj16mc304 architecture provides two methods by which program space can be accessed during operation: ? using table instructions to access individual bytes or words anywhere in the program space ? remapping a portion of the program space into the data space (program space visibility) table instructions allow an application to read or write to small areas of the program memory. this capability makes the method ideal for accessing data tables that need to be updated periodically. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. the application can only access the least significant word of the program word. 4.8.1 addressing program space since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. the solution depends on the interface method to be used. for table operations, the 8-bit table page register (tblpag) is used to define a 32k word region within the program space. this is concatenated with a 16-bit ea to arrive at a full 24-bit program space address. in this format, the most significant bit of tblpag is used to determine if the operation occurs in the user memory (tblpag<7> = 0 ) or the configuration memory (tblpag<7> = 1 ). for remapping operations, the 8-bit program space visibility register (psvpag) is used to define a 16k word page in the program space. when the most significant bit of the ea is ? 1 ?, psvpag is concatenated with the lower 15 bits of the ea to form a 23-bit program space address. unlike table operations, this limits remapping operations strictly to the user memory area. table 4-28 and figure 4-7 show how the program ea is created for table operations and remapping accesses from the data ea. here, p<23:0> refers to a program space word, and d<15:0> refers to a data space word. table 4-28: program space address construction access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx program space visibility (block remap/read) user 0 psvpag<7:0> data ea<14:0> (1) 0 xxxx xxxx xxx xxxx xxxx xxxx note 1: data ea<15> is always ? 1 ? in this case, but is not used in calcul ating the program space address. bit 15 of the address is psvpag<0>. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 52 ? 2007-2012 microchip technology inc. figure 4-7: data acc ess from program spac e address generation 0 program counter 23 bits 1 psvpag 8 bits ea 15 bits program counter (1) select tblpag 8 bits ea 16 bits byte select 0 0 1/0 user/configuration table operations (2) program space visibility (1) space select 24 bits 23 bits (remapping) 1/0 0 note 1: the least significant bit (lsb) of program space addresses is always fixed as ? 0 ? to maintain word alignment of data in the program and data spaces. 2: table operations are not required to be word -aligned. table read operations are permitted in the configuration memory space. ? 2007-2012 microchip technology inc. ds70283k-page 53 dspic33fj32mc202/204 and dspic33fj16mc304 4.8.2 data access from program memory using table instructions the tblrdl and tblwtl instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. the tblrdh and tblwth instructions are the only method to read or write the upper 8 bits of a program space word as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit-wide word address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space that contains the least significant data word. tblrdh and tblwth access the space that contains the upper data byte. two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. both function as either byte or word operations. ? tblrdl (table read low): - in word mode, this instruction maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>). - in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is ? 1 ?; the lower byte is selected when it is ? 0 ?. ? tblrdh (table read high): - in word mode, this instruction maps the entire upper word of a program address (p<23:16>) to a data address. note that d<15:8>, the ?phantom byte?, will always be ? 0 ?. - in byte mode, this inst ruction maps the upper or lower byte of the program word to d<7:0> of the data address, in the tblrdl instruc- tion. the data is always ? 0 ? when the upper ?phantom? byte is selected (byte select = 1 ). in a similar fashion, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are explained in section 5.0 ?flash program memory? . for all table operations, the area of program memory space to be accessed is determined by the table page register (tblpag). tblpag covers the entire program memory space of the device, including user and configuration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 4-8: accessing program memory with table instructions 0 8 16 23 00000000 00000000 00000000 00000000 ?phantom? byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 02 0x000000 0x800000 0x020000 0x030000 program space the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are shown; write operations are also valid in the user memory area. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 54 ? 2007-2012 microchip technology inc. 4.8.3 reading data from program memory using program space visibility the upper 32 kbytes of data space may optionally be mapped into any 16k word page of the program space. this option provides transparent access to stored constant data from the data space without the need to use special instructions (such as tblrdl/h ). program space access through the data space occurs if the most significant bit of the data space ea is ? 1 ? and program space visibility is enabled by setting the psv bit in the core control register (corcon<2>). the location of the program memory space to be mapped into the data space is determined by the program space visibility page register (psvpag). this 8-bit register defines any one of 256 possible pages of 16k words in program space. in effect, psvpag functions as the upper 8 bits of the program memory address, with the 15 bits of the ea functioning as the lower bits. by incrementing the pc by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. data reads to this area ad d a cycle to the instruction being executed, since two program memory fetches are required. although each data space address 8000h and higher maps directly into a corresponding program memory address (see figure 4-9), only the lower 16 bits of the 24-bit program word are us ed to contain the data. the upper 8 bits of any program space location used as data should be programmed with ? 1111 1111 ? or ? 0000 0000 ? to force a nop . this prevents possible issues should the area of code ever be accidentally executed. for operations that use psv and are executed outside a repeat loop, the mov and mov.d instructions require one instruction cycle in addition to the specified execution time. all other instructions require two instruction cycles in addition to the specified execution time. for operations that use psv, and are executed inside a repeat loop, these instances require two instruction cycles in addition to the spec ified execution time of the instruction: ? execution in th e first iteration ? execution in the last iteration ? execution prior to exiting the loop due to an interrupt ? execution upon re-entering the loop after an interrupt is serviced any other iteration of the repeat loop will allow the instruction using psv to access data, to execute in a single cycle. figure 4-9: program space visibility operation note: psv access is temporar ily disabled during table reads/writes. 23 15 0 psvpag data space program space 0x0000 0x8000 0xffff 02 0x000000 0x800000 0x010000 0x018000 when corcon<2> = 1 and ea<15> = 1 : the data in the page designated by psvpag is mapped into the upper half of the data memory space... data ea<14:0> ...while the lower 15 bits of the ea specify an exact address within the psv area. this corresponds exactly to the same lower 15 bits of the actual program space address. psv area ? 2007-2012 microchip technology inc. ds70283k-page 55 dspic33fj32mc202/204 and dspic33fj16mc304 5.0 flash program memory the dspic33fj32mc202/204 and dspic33fj16mc304 devices contain internal flash program memory for storing and executing application code. the memory is readable, writable and erasable during normal operation over the entire v dd range. flash memory can be programmed in two ways: ? in-circuit serial programming? (icsp?) programming capability ? run-time self-programming (rtsp) icsp allows a dspic33fj32mc202/204 and dspic33fj16mc304 device to be serially programmed while in the end application circuit. this is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: pgecx/pgedx), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. this also allows the most recent firmware or a custom firmware to be pro- grammed. rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user application can write program memory data either in blocks or ?rows? of 64 inst ructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ?pages? of 512 instructions (1536 bytes) at a time. 5.1 table instructions and flash programming regardless of the method used, all programming of flash memory is done with the table read and table write instructions. these al low direct read and write access to the program memory space from the data memory while the device is in normal operating mode. the 24-bit target address in the program memory is formed using bits <7:0> of the tblpag register and the effective address (ea) from a w register specified in the table instruction, as shown in figure 5-1 . the tblrdl and the tblwtl instructions are used to read or write to bits <15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits <23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 5-1: addressing for table registers note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 devices. it is not intended to be a comprehensive refer- ence source. to complement the infor- mation in this data sheet, refer to section 5. ?flash programming? (ds70191) of the ?dspic33f/pic24h family refer- ence manual? which is available from the microchip web site ( www.microchip.com ) 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. 0 program counter 24 bits program counter tblpag reg 8 bits working reg ea 16 bits byte 24-bit ea 0 1/0 select using table instruction using user/configuration space select dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 56 ? 2007-2012 microchip technology inc. 5.2 rtsp operation the dspic33fj32mc202/204 and dspic33fj16mc304 flash program memory array is organized into rows of 64 instructions or 192 bytes. rtsp allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. table 24-12 shows typical erase and programming times. the 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. the program memory implements holding buffers that can contain 64 instructions of programming data. prior to the actual programming operation, the write data must be loaded into the buffers sequentially. the instruction words loaded must always be from a group of 64 boundary. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the buffers. programming is performed by setting the control bits in the nvmcon register. a total of 64 tblwtl and tblwth instructions are required to load the instructions. all of the table write operat ions are single-word writes (two instruction cycles) because only the buffers are written. a programming cycle is required for programming each row. 5.3 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. the processor stalls (waits) until the programming operation is finished. the programming time depends on the frc accuracy (see table 24-18 , ? ac characteristics: internal rc accuracy ? ) and the value of the frc oscillator tuning register (see register 8-4 ). use the following formula to calculate the minimum and maximum values for the row write time, page erase time, and word write cycle time parameters (see table 24-12 , ? dc characteristics: program memory ? ). equation 5-1: programming time for example, if the devi ce is operating at +125 c, the frc accuracy will be 5%. if the tun<5:0> bits (see register 8-4 ) are set to ?b111111 ,the minimum row write time is equal to equation 5-2 . equation 5-2: minimum row write time the maximum row write time is equal to equation 5-3 . equation 5-3: maximum row write time setting the wr bit (nvmcon<15>) starts the opera- tion, and the wr bit is automatically cleared when the operation is finished. 5.4 flash memory resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 5.4.1 key resources ? section 5. ?flash programming? (ds70191) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools 5.5 control registers two sfrs are used to read and write the program flash memory: nvmcon and nvmkey. the nvmcon register ( register 5-1 ) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. nvmkey is a write-only regist er that is used for write protection. to start a pr ogramming or erase sequence, the user application must c onsecutively write 0x55 and 0xaa to the nvmkey register. refer to section 5.3 ?programming operations? for further details. t 7.37 mhz frc accuracy () % frc tuning () % --------------------------------------------------------------------------------------------------------------------------- - note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 t rw 11064 cycles 7.37 mhz 10.05 + () 1 0.00375 ? () ------------------------------------------------------------------------------------------------ 1.435 ms = = t rw 11064 cycles 7.37 mhz 10.05 ? () 1 0.00375 ? () ----------------------------------------------------------------------------------------------- - 1.586 ms = = ? 2007-2012 microchip technology inc. ds70283k-page 57 dspic33fj32mc202/204 and dspic33fj16mc304 register 5-1: nvmcon: flash memory control register r/so-0 (1) r/w-0 (1) r/w-0 (1) u-0 u-0 u-0 u-0 u-0 wr wren wrerr ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 (1) u-0 u-0 r/w-0 (1) r/w-0 (1) r/w-0 (1) r/w-0 (1) ? erase ? ?nvmop<3:0> (2) bit 7 bit 0 legend: so = settable only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 wr: write control bit 1 = initiates a flash memory program or erase operat ion. the operation is self-timed and the bit is cleared by hardware once operation is complete 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit 1 = enable flash program/erase operations 0 = inhibit flash program/erase operations bit 13 wrerr: write sequence error flag bit 1 = an improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12-7 unimplemented: read as ? 0 ? bit 6 erase: erase/program enable bit 1 = perform the erase operation specified by nvmop<3:0> on the next wr command 0 = perform the program operation specified by nvmop<3:0> on the next wr command bit 5-4 unimplemented: read as ? 0 ? bit 3-0 nvmop<3:0>: nvm operation select bits (2) if erase = 1 : 1111 = memory bulk erase operation 1101 = erase general segment 1100 = erase secure segment 0011 = no operation 0010 = memory page erase operation 0001 = no operation 0000 = erase a single configuration register byte if erase = 0 : 1111 = no operation 1101 = no operation 1100 = no operation 0011 = memory word program operation 0010 = no operation 0001 = memory row program operation 0000 = program a single configuration register byte note 1: these bits can only be reset on a por. 2: all other combinations of nv mop<3:0> are unimplemented. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 58 ? 2007-2012 microchip technology inc. register 5-2: nvmkey: nonvolatile memory key register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> bit 7 bit 0 legend: so = settable only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-0 nvmkey<7:0>: key register (w rite-only) bits ? 2007-2012 microchip technology inc. ds70283k-page 59 dspic33fj32mc202/204 and dspic33fj16mc304 5.5.1 programming algorithm for flash program memory programmers can program one row of program flash memory at a time. to do this, it is necessary to erase the 8-row erase page that contains the desired row. the general process is: 1. read eight rows of program memory (512 instructions) and store in data ram. 2. update the program data in ram with the desired new data. 3. erase the block (see example 5-1 ): a) set the nvmop bits (nvmcon<3:0>) to ? 0010 ? to configure for block erase. set the erase (nvmcon<6>) and wren (nvmcon<14>) bits. b) write the starting address of the page to be erased into the tblpag and w registers. c) write 0x55 to nvmkey. d) write 0xaa to nvmkey. e) set the wr bit (nvmcon<15>). the erase cycle begins and the cpu stalls for the duration of the erase cycle. when the erase is done, the wr bit is cleared automatically. 4. write the first 64 instructions from data ram into the program memory buffers (see example 5-2 ). 5. write the program block to flash memory: a) set the nvmop bits to ? 0001 ? to configure for row programming. clear the erase bit and set the wren bit. b) write 0x55 to nvmkey. c) write 0xaa to nvmkey. d) set the wr bit. the programming cycle begins and the cpu stalls for the duration of the write cycle. when the write to flash memory is done, the wr bit is cleared automatically. 6. repeat steps 4 and 5, using the next available 64 instructions from the block in data ram by incrementing the value in tblpag, until all 512 instructions are written back to flash memory. for protection against accidental operations, the write initiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user application must wait for the programming time until programming is complete. the two instructions following the start of the programming sequence should be nop s, as shown in example 5-3 . example 5-1: erasing a program memory page ; set up nvmcon for block erase operation mov #0x4042, w0 ; mov w0, nvmcon ; initialize nvmcon ; init pointer to row to be erased mov #tblpage(prog_addr), w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #tbloffset(prog_addr), w0 ; initialize in-page ea[15:0] pointer tblwtl w0, [w0] ; set base address of erase block disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 60 ? 2007-2012 microchip technology inc. example 5-2: loading the write buffers example 5-3: initiating a programming sequence ; set up nvmcon for row programming operations mov #0x4001, w0 ; mov w0, nvmcon ; initialize nvmcon ; set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled mov #0x0000, w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #0x6000, w0 ; an example program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0, w2 ; mov #high_byte_0, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 1st_program_word mov #low_word_1, w2 ; mov #high_byte_1, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 2nd_program_word mov #low_word_2, w2 ; mov #high_byte_2, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ? ? ? ; 63rd_program_word mov #low_word_31, w2 ; mov #high_byte_31, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the nop ; erase command is asserted ? 2007-2012 microchip technology inc. ds70283k-page 61 dspic33fj32mc202/204 and dspic33fj16mc304 6.0 resets the reset module combines all reset sources and controls the device mast er reset signal, sysrst . the following is a list of device reset sources: ? por: power-on reset ? bor: brown-out reset ?mclr : master clear pin reset ?swr: reset instruction ? wdto: watchdog timer reset ? cm: configuration mismatch reset ? trapr: trap conflict reset ? iopuwr: illegal condition device reset - illegal opcode reset - uninitialized w register reset - security reset a simplified block diagram of the reset module is shown in figure 6-1 . any active source of reset will make the sysrst signal active. on system rese t, some of the registers associated with the cpu and peripherals are forced to a known reset state and some are unaffected. all types of device reset sets a corresponding status bit in the rcon register to indicate the type of reset (see register 6-1 ). a por clears all the bits, except for the por bit (rcon<0>), that are set. th e user application can set or clear any bit at any time during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software does not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. the function of these bits is discussed in other sections of this manual. figure 6-1: reset system block diagram note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 8. ?reset? (ds70192) of the ?dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: refer to the specific peripheral section or section 3.0 ?cpu? of this manual for register reset states. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset is meaningful. mclr v dd internal regulator bor sleep or idle reset instruction wdt module glitch filter trap conflict illegal opcode uninitialized w register sysrst v dd rise detect por configuration mismatch dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 62 ? 2007-2012 microchip technology inc. 6.1 resets resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 6.1.1 key resources ? section 8. ?reset? (ds70192) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 63 dspic33fj32mc202/204 and dspic33fj16mc304 6.2 reset control registers register 6-1: rcon: re set control register (1) r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 trapr iopuwr ? ? ? ?cmvregs bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 extr swr swdten (2) wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w access reset flag bit 1 = an illegal opcode detection, an illegal address mode or uninitialized w register used as an address pointer caused a reset 0 = an illegal opcode or uninitialized w reset has not occurred bit 13-10 unimplemented: read as ? 0 ? bit 9 cm: configuration mismatch flag bit 1 = a configuration mismatch reset has occurred 0 = a configuration mismatch reset has not occurred bit 8 vregs: voltage regulator standby during sleep bit 1 = voltage regulator is active during sleep 0 = voltage regulator goes into standby mode during sleep bit 7 extr: external reset (mclr ) pin bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset (instruction) flag bit 1 = a reset instruction has been executed 0 = a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit (2) 1 = wdt is enabled 0 = wdt is disabled bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake-up from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 64 ? 2007-2012 microchip technology inc. bit 2 idle: wake-up from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-on reset has occurred 0 = a power-on reset has not occurred register 6-1: rcon: re set control register (1) (continued) note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. ? 2007-2012 microchip technology inc. ds70283k-page 65 dspic33fj32mc202/204 and dspic33fj16mc304 6.3 system reset the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices have two types of reset: ? cold reset ? warm reset a cold reset is the result of a power-on reset (por) or a brown-out reset (bor). on a cold reset, the fnosc configuration bits in the fosc device configuration register selects the device clock source. a warm reset is the result of all other reset sources, including the reset instruction. on warm reset, the device will continue to operate from the current clock source as indicated by the current oscillator selection bits (cosc<2:0>) in the oscillator control register (osccon<14:12>). the device is kept in a reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. the sequence in which this occurs is shown in figure 6-2 . table 6-1: oscillator parameters oscillator mode oscillator start-up delay oscillator start-up timer pll lock time total delay frc, frcdiv16, frcdivn t oscd ??t oscd frcpll t oscd ?t lock t oscd + t lock xt t oscd t ost ?t oscd + t ost hs t oscd t ost ?t oscd + t ost ec ???? xtpll t oscd t ost t lock t oscd + t ost + t lock hspll t oscd t ost t lock t oscd + t ost + t lock ecpll ? ? t lock t lock sosc t oscd t ost ?t oscd + t ost lprc t oscd ??t oscd note 1: t oscd = oscillator start-up delay (1.1 s max for frc, 70 s max for lprc). crystal oscillator start-up times vary with crystal characteristics, load capacitance, etc. 2: t ost = oscillator start-up timer delay (1024 oscillator clock period). for example, t ost = 102.4 s for a 10 mhz crystal and t ost = 32 ms for a 32 khz crystal. 3: t lock = pll lock time (1.5 ms nominal), if pll is enabled. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 66 ? 2007-2012 microchip technology inc. figure 6-2: system reset timing reset run device status v dd v por vbor v bor por bor sysrst t pwrt t por t bor oscillator clock t oscd t ost t lock time fscm t fscm 1 2 3 4 5 6 note 1: por: a por circuit holds the device in reset when the pow er supply is turned on. the por circuit is active until v dd crosses the v por threshold and the delay t por has elapsed. 2: bor: the on-chip voltage regulator has a bor circ uit that keeps the device in reset until v dd crosses the v bor threshold and the delay t bor has elapsed. the delay t bor ensures the voltage regulator output becomes stable. 3: pwrt timer: the programmable power-up timer continues to hold the processor in reset for a specific period of time (t pwrt ) after a bor. the delay t pwrt ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. after the delay t pwrt has elapsed, the sysrst becomes inactive, which in turn enables the selected oscillator to start generating clock cycles. 4: oscillator delay: the total delay for the clock to be ready for various clock source se lections are given in table 6-1 . refer to section 8.0 ?oscillator configuration? for more information. 5: when the oscillator cloc k is ready, the processor begins exec ution from location 0x000000. the user application programs a goto instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: the fail-safe clock monitor (fscm), if enabled, begins to monitor the system cl ock when the system clock is ready and the delay t fscm elapsed. ? 2007-2012 microchip technology inc. ds70283k-page 67 dspic33fj32mc202/204 and dspic33fj16mc304 6.4 power-on reset (por) a power-on reset (por) circuit ensures the device is reset from power-on. the por circuit is active until v dd crosses the v por threshold and the delay t por has elapsed. the delay t por ensures the internal device bias circuits become stable. the device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the por. refer to section 24.0 ?electrical characteristics? for details. the por status bit (por) in the reset control register (rcon<0>) is set to indicate the power-on reset. 6.4.1 brown-out reset (bor) and power-up timer (pwrt) the on-chip regulator has a brown-out reset (bor) circuit that resets the device when the v dd is too low (v dd < v bor ) for proper device operation. the bor circuit keeps the device in reset until v dd crosses v bor threshold and the delay t bor has elapsed. the delay t bor ensures the voltage regulator output becomes stable. the bor status bit (bor) in the reset control register (rcon<1>) is set to indicate the brown-out reset. the device will not run at full speed after a bor as the v dd should rise to acceptab le levels for full-speed operation. the pwrt provides power-up time delay (t pwrt ) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the sysrst is released. the power-up timer delay (t pwrt ) is programmed by the power-on reset timer value select bits (fpwrt<2:0>) in the por configuration register (fpor<2:0>), which provides eight settings (from 0 ms to 128 ms). refer to section 21.0 ?special features? for further details. figure 6-3 shows the typical brown-out scenarios. the reset delay (t bor + t pwrt ) is initiated each time v dd rises above the v bor trip point table 6-2: oscillator delay symbol parameter value v por por threshold 1.8v nominal t por por extension time 30 s maximum v bor bor threshold 2.5v nominal t bor bor extension time 100 s maximum t pwrt programmable power-up time delay 0-128 ms nominal t fscm fail-safe clock monitor delay 900 s maximum note: when the device exits the reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperat ure, etc.) must be within their operat ing ranges, other- wise the device may not function cor- rectly. the user application must ensure that the delay between the time power is first applied, and the time sysrst becomes inactive, is long enough to get all operating parameters within specification. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 68 ? 2007-2012 microchip technology inc. figure 6-3: brown-out situations 6.5 external reset (extr) the external reset is generated by driving the mclr pin low. the mclr pin is a schmitt trigger input with an additional glitch filter. reset pulses that are longer than the minimum pulse-width will generate a reset. refer to section 24.0 ?electri cal characteristics? for minimum pulse-width specifications. the external reset (mclr ) pin (extr) bit in the reset control register (rcon) is set to indicate the mclr reset. 6.5.1 external super visory circuit many systems have external supervisory circuits that generate reset signals to reset multiple devices in the system. this external reset signal can be directly connected to the mclr pin to reset the device when the rest of system is reset. 6.5.2 internal supervisory circuit when using the internal power supervisory circuit to reset the device, the external reset pin (mclr ) should be tied directly or resistively to v dd . in this case, the mclr pin will not be used to generate a reset. the external reset pin (mclr ) does not have an internal pull-up and must not be left unconnected. 6.6 software reset instruction (swr) whenever the reset instruction is executed, the device will assert sysrst , placing the device in a special reset state. this reset state will not re-initialize the clock. the clock source in effect prior to the reset instruction will remain. sysrst is released at the next instruction cycle, and the reset vector fetch will commence. the software reset (instruction) flag (swr) bit in the reset control register (rco n<6>) is set to indicate the software reset. 6.7 watchdog time-out reset (wdto) whenever a watchdog time-out occurs, the device will asynchronously assert sysrst . the clock source will remain unchanged. a wdt time-out during sleep or idle mode will wake-up the processor, but will not reset the processor. the watchdog timer time-out flag bit (wdto) in the reset control register (rco n<4>) is set to indicate the watchdog reset. refer to section 21.4 ?watchdog timer (wdt)? for more information on watchdog reset. 6.8 trap conflict reset if a lower-priority hard trap occurs while a higher-priority trap is being processed, a hard trap conflict reset occurs. the hard traps include exceptions of priority level 13 through level 15, inclusive. the address error (level 13) and oscillator error (level 14) traps fall into this category. the trap reset flag bit (trapr) in the reset control register (rcon<15>) is set to indicate the trap conflict reset. refer to section 7.0 ?interrupt controller? for more information on tr ap conflict resets. v dd sysrst v bor v dd sysrst v bor v dd sysrst v bor t bor + t pwrt v dd dips before pwrt expires t bor + t pwrt t bor + t pwrt ? 2007-2012 microchip technology inc. ds70283k-page 69 dspic33fj32mc202/204 and dspic33fj16mc304 6.9 configuration mismatch reset to maintain the integrity of the peripheral pin select control registers, they ar e constantly monitored with shadow registers in hardware. if an unexpected change in any of the registers occur (such as cell disturbances caused by esd or other external events), a configuration mismatch reset occurs. the configuration mismatch flag bit (cm) in the reset control register (rcon<9>) is set to indicate the configuration mismatch reset. refer to section 10.0 ?i/o ports? for more information on the configuration mismatch reset. 6.10 illegal condition device reset an illegal condition device reset occurs due to the following sources: ? illegal opcode reset ? uninitialized w register reset ? security reset the illegal opcode or uninitialized w access reset flag bit (iopuwr) in the reset control register (rcon<14>) is set to indicate the illegal condition device reset. 6.10.1 illegal opcode reset a device reset is generated if the device attempts to execute an illegal opcode va lue that is fetched from program memory. the illegal opcode reset function can prevent the device from executing progr am memory sections that are used to store constant data. to take advantage of the illegal opcode reset, use only the lower 16 bits of each program memory section to store the data values. the upper 8 bits should be programmed with 3fh, which is an illegal opcode value. 6.10.2 uninitialized w register reset any attempts to use the uninitialized w register as an address pointer will reset the device. the w register array (with the exception of w15) is cleared during all resets and is considered unin itialized until written to. 6.10.3 security reset if a program flow change (pfc) or vector flow change (vfc) targets a restricted location in a protected segment (boot and secure segment), that operation will cause a security reset. the pfc occurs when the program counter is reloaded as a result of a call, jump, computed jump, return, return from subroutine, or other form of branch instruction. the vfc occurs when the program counter is reloaded with an interrupt or trap vector. refer to section 21.8 ?code protection and codeguard? security? for more information on security reset. 6.11 using the rcon status bits the user application can read the reset control regis- ter (rcon) after any device reset to determine the cause of the reset. table 6-3 provides a summary of the reset flag bit operation. table 6-3: reset flag bit operation note: the configuration mi smatch feature and associated reset flag is not available on all devices. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset will be meaningful. flag bit set by: cleared by: trapr (rcon<15>) trap conflict event por,bor iopwr (rcon<14>) illegal opcode or uninitialized w register access or security reset por,bor cm (rcon<9>) configuration mismatch por,bor extr (rcon<7>) mclr reset por swr (rcon<6>) reset instruction por,bor wdto (rcon<4>) wdt time-out pwrsav instruction, clrwdt instruction, por,bor sleep (rcon<3>) pwrsav #sleep instruction por,bor idle (rcon<2>) pwrsav #idle instruction por,bor bor (rcon<1>) por, bor ? por (rcon<0>) por ? note: all reset flag bits can be set or cleared by user software. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 70 ? 2007-2012 microchip technology inc. notes: ? 2007-2012 microchip technology inc. ds70283k-page 71 dspic33fj32mc202/204 and dspic33fj16mc304 7.0 interrupt controller the dspic33fj32mc202/204 and dspic33fj16mc304 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dspic33fj32mc202/204 and dspic33fj16mc304 cpu. it has the following features: ? up to 8 processor exceptions and software traps ? 7 user-selectable priority levels ? interrupt vector table (i vt) with up to 118 vectors ? a unique vector for each interrupt or exception source ? fixed priority within a specified user priority level ? alternate interrupt vector table (aivt) for debug support ? fixed interrupt entry and return latencies 7.1 interrupt vector table the interrupt vector table (ivt) is shown in figure 7-1 . the ivt resides in program memory, starting at location 000004h. the ivt contains 126 vectors consisting of 8 nonmaskable trap vectors plus up to 118 sources of interrupt. in general , each interrupt so urce has its own vector. each interrupt vect or contains a 24-bit-wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority. this priority is linked to their position in the vector table. lower addresses generally have a higher natural priority. for example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. dspic33fj32mc202/204 and dspic33fj16mc304 devices implement up to 26 unique interrupts and 4 nonmaskable traps. these are summarized in table 7-1 and ta b l e 7 - 2 . 7.1.1 alternate interrupt vector ta b l e the alternate interrupt vector table (aivt) is located after the ivt, as shown in figure 7-1 . access to the aivt is provided by the altivt control bit (intcon2<15>). if the altivt bit is set, all interrupt and exception processes use the alternate vectors instead of the default vector s. the alternate vectors are organized in the same manner as the default vectors. the aivt supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. this feat ure also enables switching between applications for evaluation of different software algorithms at run time. if the aivt is not needed, the aivt should be programmed with the same addresses used in the ivt. 7.2 reset sequence a device reset is not a true exception because the interrupt controller is not involved in the reset process. the dspic33fj32mc202/204 and dspic33fj16mc304 device clears its registers in response to a reset, which forces the pc to zero. the digital signal controller then begins program execution at location 0x000000. a goto instruction at the reset address can redirect program execution to the appropriate start-up routine. note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 devices. it is not intended to be a comprehensive refer- ence source. to complement the infor- mation in this data sheet, refer to section 32. ?interrupts (part iii)? (ds70214) of the ? dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: any unimplemented or unused vector locations in the ivt and aivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 72 ? 2007-2012 microchip technology inc. figure 7-1: ds pic33fj32mc202/204 and dspic33fj16 mc304 interrupt vector table reset ? goto instruction 0x000000 reset ? goto address 0x000002 reserved 0x000004 oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 0x000014 interrupt vector 1 ~ ~ ~ interrupt vector 52 0x00007c interrupt vector 53 0x00007e interrupt vector 54 0x000080 ~ ~ ~ interrupt vector 116 0x0000fc interrupt vector 117 0x0000fe reserved 0x000100 reserved 0x000102 reserved oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 0x000114 interrupt vector 1 ~ ~ ~ interrupt vector 52 0x00017c interrupt vector 53 0x00017e interrupt vector 54 0x000180 ~ ~ ~ interrupt vector 116 interrupt vector 117 0x0001fe start of code 0x000200 decreasing natural order priority interrupt vector table (ivt) (1) alternate interrupt vector table (aivt) (1) note 1: see table 7-1 for the list of implemented interrupt vectors. ? 2007-2012 microchip technology inc. ds70283k-page 73 dspic33fj32mc202/204 and dspic33fj16mc304 table 7-2: trap vectors table 7-1: interrupt vectors vector number interrupt request (irq) number ivt address aivt address interrupt source 8 0 0x000014 0x000114 int0 ? external interrupt 0 9 1 0x000016 0x000116 ic1 ? input capture 1 10 2 0x000018 0x000118 oc1 ? output compare 1 11 3 0x00001a 0x00011a t1 ? timer1 12 4 0x00001c 0x00011c reserved 13 5 0x00001e 0x00011e ic2 ? input capture 2 14 6 0x000020 0x000120 oc2 ? output compare 2 15 7 0x000022 0x000122 t2 ? timer2 16 8 0x000024 0x000124 t3 ? timer3 17 9 0x000026 0x000126 spi1e ? spi1 error 18 10 0x000028 0x000128 spi1 ? spi1 transfer done 19 11 0x00002a 0x00012a u1rx ? uart1 receiver 20 12 0x00002c 0x00012c u1tx ? uart1 transmitter 21 13 0x00002e 0x00012e adc1 ? adc1 22-23 14-15 0x000030-0x000032 0x000130-0x000132 reserved 24 16 0x000034 0x000134 si2c1 ? i2c1 slave events 25 17 0x000036 0x000136 mi2c1 ? i2c1 master events 26 18 0x000038 0x000138 reserved 27 19 0x00003a 0x00013a change notification interrupt 28 20 0x00003c 0x00013c int1 ? external interrupt 1 29 21 0x00003e 0x00013e reserved 30 22 0x000040 0x000140 ic7 ? input capture 7 31 23 0x000042 0x000142 ic8 ? input capture 8 32-36 24-28 0x000044-0x00004c 0x000144-0x00014c reserved 37 29 0x00004e 0x00014e int2 ? external interrupt 2 38-64 30-56 0x000050-0x000084 0x000150-0x000184 reserved 65 57 0x000086 0x000186 pwm1 ? pwm1 period match 66 58 0x000088 0x000188 qei ? position counter compare 67-70 59-62 0x00008a-0x000090 0x00018a-0x000190 reserved 71 63 0x000092 0x000192 flta1 ? pwm1 fault a 72 64 0x000094 0x000194 reserved 73 65 0x000096 0x000196 u1e ? uart1 error 74-80 66-72 0x000098-0x0000a4 0x000198-0x0001a4 reserved 81 73 0x0000a6 0x0001a6 pwm2 ? pwm2 period match 82 74 0x0000a8 0x0001a8 flta2 ? pwm2 fault a 83-125 75-117 0x0000aa-0x0000fe 0x0001aa-0x0001fe reserved vector number ivt address aivt address trap source 0 0x000004 0x000104 reserved 1 0x000006 0x000106 oscillator failure 2 0x000008 0x000108 address error 3 0x00000a 0x00010a stack error 4 0x00000c 0x00010c math error 5 0x00000e 0x00010e reserved 6 0x000010 0x000110 reserved 7 0x000012 0x000112 reserved dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 74 ? 2007-2012 microchip technology inc. 7.3 interrupt resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 7.3.1 key resources ? section 6. ?interrupts? (ds70184) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools 7.4 interrupt control and status registers dspic33fj32mc202/204 and dspic33fj16mc304 devices implement a total of 22 registers for the interrupt controller: ? intcon1 ? intcon2 ?ifsx ?iecx ?ipcx ?inttreg 7.4.1 intcon1 and intcon2 global interrupt control functions are controlled from intcon1 and intcon2. intcon1 contains the interrupt nesting disable bit (nstdis) as well as the control and status flags for the processor trap sources. the intcon2 register contro ls the external interrupt request signal behavior and the use of the alternate interrupt vector table. 7.4.2 ifsx the ifs registers maintain all of the interrupt request flags. each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.4.3 iecx the iec registers maintain all of the interrupt enable bits. these control bits are used to individually enable interrupts from the peripherals or external signals. 7.4.4 ipcx the ipc registers are used to set the interrupt priority level for each source of interrupt. each user interrupt source can be assigned to one of eight priority levels. 7.4.5 inttreg the inttreg register contains the associated interrupt vector number and the new cpu interrupt priority level, which are latched into vector number (vecnum<6:0>) and interrupt level bit (ilr<3:0>) fields in the inttreg register. the new interrupt priority level is the priority of the pending interrupt. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the same sequence that they are listed in ta b l e 7 - 1 . for example, the int0 (external interrupt 0) is shown as having vector number 8 and a natural order priority of 0. thus, the int0if bit is found in ifs0<0>, the int0ie bit in iec0<0>, and the int0ip bits in the first position of ipc0 (ipc0<2:0>). 7.4.6 status/control registers although they are not specific ally part of the interrupt control hardware, two of the cpu control registers contain bits that contro l interrupt functionality. ? the cpu status register, sr, contains the ipl<2:0> bits (sr<7:5>). these bits indicate the current cpu interrupt priority level. the user can change the current cpu priority level by writing to the ipl bits. ? the corcon register contains the ipl3 bit which, together with ipl<2:0>, also indicates the current cpu priority level. ipl3 is a read-only bit so that trap events cannot be masked by the user software. all interrupt registers are described in register 7-1 through register 7-24 in the following pages. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 75 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-1: sr: cpu status register (1) r-0 r-0 r/c-0 r/c-0 r-0 r/c-0 r -0 r/w-0 oa ob sa sb oab sab da dc bit 15 bit 8 r/w-0 (3) r/w-0 (3) r/w-0 (3) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl2 (2) ipl1 (2) ipl0 (2) ra n ov z c bit 7 bit 0 legend: c = clear only bit r = readable bit u = unimplemented bit, read as ?0? s = set only bit w = writable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (2) 111 = cpu interrupt priority level is 7 (15), user interrupts disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: for complete register details, see register 3-1: ?sr: cpu status register? . 2: the ipl<2:0> bits are concatenated with the ipl<3> bi t (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read -only when nstdis (intcon1<15>) = 1 . register 7-2: corcon: core control register (1) u-0 u-0 u-0 r/w-0 r/w-0 r-0 r-0 r-0 ? ? ?usedt dl<2:0> bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r/w-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 (2) psv rnd if bit 7 bit 0 legend: c = clear only bit r = readable bit w = writable bit -n = value at por ?1? = bit is set 0? = bit is cleared ?x = bit is unknown u = unimplemented bit, read as ?0? bit 3 ipl3: cpu interrupt priority level status bit 3 (2) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: for complete register details, see register 3-2: ?corcon: core control register? . 2: the ipl3 bit is concatenated with t he ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 76 ? 2007-2012 microchip technology inc. register 7-3: intcon1: interrupt control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 sftacerr div0err ? matherr addrerr stkerr oscfail ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14 ovaerr: accumulator a overflow trap flag bit 1 = trap was caused by overflow of accumulator a 0 = trap was not caused by overflow of accumulator a bit 13 ovberr: accumulator b overflow trap flag bit 1 = trap was caused by overflow of accumulator b 0 = trap was not caused by overflow of accumulator b bit 12 covaerr: accumulator a catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator a 0 = trap was not caused by catastrophic overflow of accumulator a bit 11 covberr: accumulator b catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator b 0 = trap was not caused by catastrophic overflow of accumulator b bit 10 ovate: accumulator a overflow trap enable bit 1 = trap overflow of accumulator a 0 = trap disabled bit 9 ovbte: accumulator b overflow trap enable bit 1 = trap overflow of accumulator b 0 = trap disabled bit 8 covte: catastrophic overflow trap enable bit 1 = trap on catastrophic overflow of accumulator a or b enabled 0 = trap disabled bit 7 sftacerr: shift accumulator error status bit 1 = math error trap was caused by an invalid a ccumulator shift 0 = math error trap was not caused by an invalid accumulator shift bit 6 div0err: arithmetic error status bit 1 = math error trap was caused by a divide by zero 0 = math error trap was not caused by a divide by zero bit 5 unimplemented: read as ? 0 ? bit 4 matherr: arithmetic error status bit 1 = math error trap has occurred 0 = math error trap has not occurred bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred ? 2007-2012 microchip technology inc. ds70283k-page 77 dspic33fj32mc202/204 and dspic33fj16mc304 bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as ? 0 ? register 7-3: intcon1: interrupt control register 1 (continued) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 78 ? 2007-2012 microchip technology inc. register 7-4: intcon2: interrupt control register 2 r/w-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 altivt disi ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? int2ep int1ep int0ep bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 altivt: enable alternate interrupt vector table bit 1 = use alternate vector table 0 = use standard (default) vector table bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13-3 unimplemented: read as ? 0 ? bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge ? 2007-2012 microchip technology inc. ds70283k-page 79 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-5: ifs0: interrupt flag status register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ad1if u1txif u1rxif spi1if spi1eif t3if bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2if oc2if ic2if ? t1if oc1if ic1if int0if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ad1if: adc1 conversion complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 u1txif: uart1 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 u1rxif: uart1 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 spi1if: spi1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 spi1eif: spi1 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 t3if: timer3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 t2if: timer2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 oc2if: output compare channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic2if: input capture channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 unimplemented: read as ? 0 ? bit 3 t1if: timer1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 oc1if: output compare channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 80 ? 2007-2012 microchip technology inc. bit 1 ic1if: input capture channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 int0if: external interrupt 0 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 7-5: ifs0: interrupt flag status register 0 (continued) ? 2007-2012 microchip technology inc. ds70283k-page 81 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-6: ifs1: interrupt flag status register 1 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?int2if ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 ic8if ic7if ? int1if cnif ? mi2c1if si2c1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 int2if: external interrupt 2 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12-8 unimplemented: read as ? 0 ? bit 7 ic8if: input capture channel 8 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 ic7if: input capture channel 7 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 unimplemented: read as ? 0 ? bit 4 int1if: external interrupt 1 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 cnif: input change notification interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 unimplemented: read as ? 0 ? bit 1 mi2c1if: i2c1 master events in terrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 si2c1if: i2c1 slave events interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 82 ? 2007-2012 microchip technology inc. register 7-7: ifs3: interrupt flag status register 3 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 flta1if ? ? ? ? qeiif pwm1if ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 flta1if: pwm1 fault a interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14-11 unimplemented: read as ? 0 ? bit 10 qeiif: qei event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 pwm1if: pwm1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8-0 unimplemented: read as ? 0 ? ? 2007-2012 microchip technology inc. ds70283k-page 83 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-8: ifs4: interrupt flag status register 4 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 ? ? ? ? ? flta2if pwm2if ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 ? ? ? ? ? ?u1eif ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10 flta2if: pwm2 fault a interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 pwm2if: pwm2 error interrupt enable bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8-2 unimplemented: read as ? 0 ? bit 1 u1eif: uart1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as ? 0 ? dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 84 ? 2007-2012 microchip technology inc. register 7-9: iec0: interrupt enable control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ad1ie u1txie u1rxie spi1ie spi1eie t3ie bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ad1ie: adc1 conversion complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12 u1txie: uart1 transmitter interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 11 u1rxie: uart1 receiver interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 10 spi1ie: spi1 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 spi1eie: spi1 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8 t3ie: timer3 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 7 t2ie: timer2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 oc2ie: output compare channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 ic2ie: input capture channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4 unimplemented: read as ? 0 ? bit 3 t1ie: timer1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 oc1ie: output compare channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled ? 2007-2012 microchip technology inc. ds70283k-page 85 dspic33fj32mc202/204 and dspic33fj16mc304 bit 1 ic1ie: input capture channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 int0ie: external interrupt 0 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled register 7-9: iec0: interrupt enable control register 0 (continued) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 86 ? 2007-2012 microchip technology inc. register 7-10: iec1: interrupt enable control register 1 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?int2ie ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 ic8ie ic7ie ? int1ie cnie ?mi2c1iesi2c1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 int2ie: external interrupt 2 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12-8 unimplemented: read as ? 0 ? bit 7 ic8ie: input capture channel 8 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 ic7ie: input capture channel 7 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 unimplemented: read as ? 0 ? bit 4 int1ie: external interrupt 1 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 3 cnie: input change notification interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 unimplemented: read as ? 0 ? bit 1 mi2c1ie: i2c1 master events interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 si2c1ie: i2c1 slave events interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled ? 2007-2012 microchip technology inc. ds70283k-page 87 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-11: iec3: interrupt enable control register 3 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 flta1ie ? ? ? ? qeiie pwm1ie ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 flta1ie: pwm1 fault a interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 14-11 unimplemented: read as ? 0 ? bit 10 qeiie: qei event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 pwm1ie: pwm1 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8-0 unimplemented: read as ? 0 ? dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 88 ? 2007-2012 microchip technology inc. register 7-12: iec4: interrupt enable control register 4 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 ? ? ? ? ? fla2ie pwm2ie ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 ? ? ? ? ? ?u1eie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10 fla2ie: pwm2 fault a interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 pwm2ie: pwm2 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8-2 unimplemented: read as ? 0 ? bit 1 u1eie: uart1 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 unimplemented: read as ? 0 ? ? 2007-2012 microchip technology inc. ds70283k-page 89 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-13: ipc0: interrupt priority control register 0 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t1ip<2:0> ?oc1ip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ?ic1ip<2:0> ? int0ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t1ip<2:0>: timer1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc1ip<2:0>: output compare channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic1ip<2:0>: input capture channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 int0ip<2:0>: external interrupt 0 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 90 ? 2007-2012 microchip technology inc. register 7-14: ipc1: interrupt priority control register 1 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t2ip<2:0> ?oc2ip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ?ic2ip<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t2ip<2:0>: timer2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc2ip<2:0>: output compare channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic2ip<2:0>: input capture channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ? ? 2007-2012 microchip technology inc. ds70283k-page 91 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-15: ipc2: interrupt priority control register 2 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u1rxip<2:0> ? spi1ip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spi1eip<2:0> ? t3ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u1rxip<2:0>: uart1 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 spi1ip<2:0>: spi1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 spi1eip<2:0>: spi1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t3ip<2:0>: timer3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 92 ? 2007-2012 microchip technology inc. register 7-16: ipc3: interrupt priority control register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ?ad1ip<2:0> ? u1txip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ad1ip<2:0>: adc1 conversion complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 u1txip<2:0>: uart1 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled ? 2007-2012 microchip technology inc. ds70283k-page 93 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-17: ipc4: interrupt priority control register 4 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? cnip<2:0> ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? mi2c1ip<2:0> ? si2c1ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cnip<2:0>: change notification interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11-7 unimplemented: read as ? 0 ? bit 6-4 mi2c1ip<2:0>: i2c1 master events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 si2c1ip<2:0>: i2c1 slave events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 94 ? 2007-2012 microchip technology inc. register 7-18: ipc5: interrupt priority control register 5 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ?ic8ip<2:0> ? ic7ip<2:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? int1ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 ic8ip<2:0>: input capture channel 8 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 ic7ip<2:0>: input capture channel 7 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-3 unimplemented: read as ? 0 ? bit 2-0 int1ip<2:0>: external interrupt 1 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled ? 2007-2012 microchip technology inc. ds70283k-page 95 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-19: ipc7: interrupt priority control register 7 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? int2ip<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 int2ip<2:0>: external interrupt 2 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ? dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 96 ? 2007-2012 microchip technology inc. register 7-20: ipc14: interrupt priority control register 14 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ?qeiip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? pwm1ip<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 10-8 qeiip<2:0>: qei interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 pwm1ip<2:0>: pwm1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ? ? 2007-2012 microchip technology inc. ds70283k-page 97 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-21: ipc15: interrupt priority control register 15 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ?flta1ip<2:0> ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 flta1ip<2:0>: pwm1 fault a interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11-0 unimplemented: read as ? 0 ? register 7-22: ipc16: interrupt priority control register 16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ?u1eip<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 u1eip<2:0>: uart1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ? dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 98 ? 2007-2012 microchip technology inc. register 7-23: ipc18: interrupt priority control register 18 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? flta2ip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? pwm2ip<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 8-10 flta2ip<2:0>: pwm2 fault a interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 pwm2ip<2:0>: pwm2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ? ? 2007-2012 microchip technology inc. ds70283k-page 99 dspic33fj32mc202/204 and dspic33fj16mc304 register 7-24: inttreg: interrup t control and status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ?ilr<3:0> bit 15 bit 8 u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? vecnum<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-8 ilr<3:0>: new cpu interrupt priority level bits 1111 = cpu interrupt priority level is 15 ? ? ? 0001 = cpu interrupt priority level is 1 0000 = cpu interrupt priority level is 0 bit 7 unimplemented: read as ? 0 ? bit 6-0 vecnum<6:0>: vector number of pending interrupt bits 0111111 = interrupt vector pending is number 135 ? ? ? 0000001 = interrupt vector pending is number 9 0000000 = interrupt vector pending is number 8 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 100 ? 2007-2012 microchip technology inc. 7.5 interrupt setup procedures 7.5.1 initialization to configure an interrupt source at initialization: 1. set the nstdis bit (intcon1<15>) if nested interrupts are not desired. 2. select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate ipcx register. the priority level will depend on the specific application and type of interrupt source. if multiple priority levels are not desired, the ipcx register control bits for all enabled interrupt sources can be programmed to the same non-zero value. 3. clear the interrupt flag status bit associated with the peripheral in the associated ifsx register. 4. enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate iecx register. 7.5.2 interrupt service routine the method used to declare an interrupt service rou- tine (isr) and initialize the ivt with the correct vector address depends on the programming language (c or assembler) and the language development tool suite used to develop the application. in general, the user application must clear the interrupt flag in the appropriate ifsx register for the source of interrupt that the isr handl es. otherwise, program will re-enter the isr immediately after exiting th e routine. if the isr is coded in assembly language, it must be terminated using a retfie instruction to unstack the saved pc value, srl value and old cpu priority level. 7.5.3 trap service routine a trap service routine (tsr) is coded like an isr, except that the appropriate trap status flag in the intcon1 register must be cleared to avoid re-entry into the tsr. 7.5.4 interrupt disable all user interrupts can be disabled using this procedure: 1. push the current sr value onto the software stack using the push instruction. 2. force the cpu to priority level 7 by inclusive oring the value oeh with srl. to enable user interrupts, the pop instruction can be used to restore the previous sr value. the disi instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. level 7 interrupt sources are not disabled by the disi instruction. note: at a device reset, the ipcx registers are initialized such that all user interrupt sources are assigned to priority level 4. note: only user interrupts with a priority level of 7 or lower can be disabled. trap sources (level 8-level 15) cannot be disabled. ? 2007-2012 microchip technology inc. ds70283k-page 101 dspic33fj32mc202/204 and dspic33fj16mc304 8.0 oscillator configuration the oscillator system for dspic33fj32mc202/204 and dspic33fj16mc304 devices provides: ? external and internal oscillator options as clock sources. ? an on-chip phase-locked loop (pll) to scale the internal operating frequency to the required system clock frequency. ? an internal frc oscillator that can also be used with the pll, thereby allowing full-speed operation without any external clock generation hardware. ? clock switching between various clock sources. ? programmable clock post scaler for system power savings. ? a fail-safe clock monitor (fscm) that detects clock failure and takes fail-safe measures. ? a clock control register (osccon). ? nonvolatile configuration bits for main oscillator selection. a simplified diagram of the oscillator system is shown in figure 8-1 . figure 8-1: dspic33fj32mc202/ 204 and dspic33fj 16mc304 oscillator system diagram note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 devices. it is not intended to be a comprehensive refer- ence source. to complement the infor- mation in this data sheet, refer to section 7. ?oscillator? (ds70186) of the dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note 1: see figure 8-2 for pll details. 2: if the oscillator is used with xt or hs modes, an external parallel resistor with the value of 1 m must be connected. 3: the term f p refers to the clock source for all of the peripherals, while f cy refers to the clock source for the cpu. throughout this document, f cy and f p are used interchangeably, except in the case of doze mode. f p and f cy will be different when doze mode is used with any ratio other than 1:1 which is the default. secondary oscillator (s osc ) lposcen sosco timer 1 xtpll, hspll, xt, hs, ec frcdiv<2:0> wdt, pwrt, fscm frcdivn sosc frcdiv16 ecpll, frcpll nosc<2:0> fnosc<2:0> reset frc oscillator lprc oscillator doze<2:0> s3 s1 s2 s1/s3 s7 s6 frc lprc s0 s5 s4 16 clock switch s7 clock fail 2 tun<5:0> pll (1) f cy (3) f osc frcdiv doze osc2 osc1 primary oscillator (p osc ) r (2) poscmd<1:0> f p (3) sosci dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 102 ? 2007-2012 microchip technology inc. 8.1 cpu clocking system the dspic33fj32mc202/204 and dspic33fj16mc304 devices provide seven system clock options: ? fast rc (frc) oscillator ? frc oscillator with pll ? primary (xt, hs or ec) oscillator ? primary oscillator with pll ? secondary (lp) oscillator ? low-power rc (lprc) oscillator ? frc oscillator with postscaler 8.1.1 system clock sources 8.1.1.1 fast rc the fast rc (frc) internal oscillator runs at a nominal frequency of 7.37 mhz. user software can tune the frc frequency. user software can optionally specify a factor (ranging from 1:2 to 1:256) by which the frc clock frequency is divided. th is factor is selected using the frcdiv<2:0> bits (clkdiv<10:8>). 8.1.1.2 primary the primary oscillator can use one of the following as its clock source: ? xt (crystal): crystals a nd ceramic resonators in the range of 3 mhz to 10 mhz. the crystal is connected to the osc1 and osc2 pins. ? hs (high-speed crystal): crystals in the range of 10 mhz to 40 mhz. the crystal is connected to the osc1 and osc2 pins. ? ec (external clock): the external clock signal is directly applied to the osc1 pin. 8.1.1.3 secondary the secondary (lp) oscillator is designed for low power and uses a 32.768 khz crystal or ceramic resonator. the lp oscillator uses the sosci and sosco pins. 8.1.1.4 low-power rc the lprc (low-power rc) inter nal oscillator runs at a nominal frequency of 32.768 khz. it is also used as a reference clock by the watchdog timer (wdt) and fail-safe clock monitor (fscm). 8.1.1.5 frc the clock signals generated by the frc and primary oscillators can be optionally applied to an on-chip phase locked loop (pll) to provide a wide range of output frequencies for device operation. pll configuration is described in section 8.1.3 ?pll configuration? . the frc frequency depends on the frc accuracy (see table 24-18 ) and the value of the frc oscillator tuning register (see register 8-4 ). 8.1.2 system clock selection the oscillator source used at a device power-on reset event is selected using configuration bit settings. the oscillator configuration bit settings are located in the configuration registers in the program memory. (refer to section 21.1 ?configuration bits? for further details.) the initial oscillator selection configuration bits, fnosc<2:0> (foscsel<2:0>), and the primary oscillator mode select configuration bits, poscmd<1:0> (fosc<1:0>), select the osc illator source that is used at a power-on reset. the frc primary oscillator is the default (unprogrammed) selection. the configuration bits allow users to choose among 12 different clock modes, shown in ta b l e 8 - 1 . the output of the oscillator (or the output of the pll if a pll mode has been selected) f osc is divided by 2 to generate the device instruction clock (f cy ) and the peripheral clock time base (f p ). f cy defines the operating speed of the dev ice, and speeds up to 40 mhz are supported by the dspic33fj32mc202/204 and dspic33fj16mc304 architecture. instruction execution speed or device operating frequency, f cy , is given by: equation 8-1: device operating frequency 8.1.3 pll configuration the primary oscillator and internal frc oscillator can optionally use an on-chip pll to obtain higher speeds of operation. the pll provides significant flexibility in selecting the device operating speed. a block diagram of the pll is shown in figure 8-2 . the output of the pr imary oscillator or frc, denoted as ?f in ?, is divided down by a pre scale factor (n1) of 2, 3, ... or 33 before being provided to the pll?s voltage controlled oscillator (vco). the input to the vco must be selected in the range of 0.8 mhz to 8 mhz. the prescale factor ?n1? is selected using the pllpre<4:0> bits (clkdiv<4:0>). the pll feedback divisor, selected using the plldiv<8:0> bits (pllfbd<8:0>), provides a factor ?m?, by which the input to the vco is multiplied. this factor must be selected such that the resulting vco output frequency is in the range of 100 mhz to 200 mhz. the vco output is further divided by a postscale factor ?n2.? this factor is selected using the pllpost<1:0> bits (clkdiv<7:6>). ?n2? can be either 2, 4 or 8, and must be selected such that the pll output frequency (f osc ) is in the range of 12 .5 mhz to 80 mhz, which generates device operating speeds of 6.25-40 mips. f cy f osc 2 ------------- = ? 2007-2012 microchip technology inc. ds70283k-page 103 dspic33fj32mc202/204 and dspic33fj16mc304 for a primary oscillator or frc oscillator, output ?f in ?, the pll output ?f osc ? is given by: equation 8-2: f osc calculation for example, suppose a 10 mhz crystal is being used with the selected oscillat or mode of xt with pll. ? if pllpre<4:0> = 0 , then n1 = 2. this yields a vco input of 10/2 = 5 mhz, which is within the acceptable range of 0.8-8 mhz. ? if plldiv<8:0> = 0x1e, then m = 32. this yields a vco output of 5 x 32 = 160 mhz, which is within the 100-200 mhz ranged needed. ? if pllpost<1:0> = 0 , then n2 = 2. this provides a fosc of 160/2 = 80 mhz. the resultant device operating speed is 80/2 = 40 mips. equation 8-3: xt with pll mode example figure 8-2: dspic33fj32mc202/204 and dspic33fj16mc304 pll block diagram table 8-1: configuration bi t values for clock selection f osc f in m n 1 n 2 ? --------------------- - ?? ?? ? = f cy f osc 2 ------------- 1 2 -- - 10000000 32 ? 22 ? ------------------------------------ - ?? ?? 40 mips = ? == oscillator mode oscillator source poscmd<1:0> fnosc<2:0> see note fast rc oscillator with divide-by-n (frcdivn) internal xx 111 1, 2 fast rc oscillator with divide-by-16 (frcdiv16) internal xx 110 1 low-power rc oscillator (lprc) internal xx 101 1 secondary (timer1) oscillator (sosc) secondary xx 100 1 primary oscillator (hs) with pll (hspll) primary 10 011 ? primary oscillator (xt) with pll (xtpll) primary 01 011 ? primary oscillator (ec) with pll (ecpll) primary 00 011 1 primary oscillator (hs) primary 10 010 ? primary oscillator (xt) primary 01 010 ? primary oscillator (ec) primary 00 010 1 fast rc oscillator with pll (frcpll) internal xx 001 1 fast rc oscillator (frc) internal xx 000 1 note 1: osc2 pin function is determined by the osciofnc configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device. 0.8-8.0 mhz here (1) 100-200 mhz here (1) divide by 2, 4, 8 divide by 2-513 divide by 2-33 source (crystal, external clock pllpre x vco plldiv pllpost or internal rc) 12.5-80 mhz here (1) f osc note 1: this frequency range must be satisfied at all times. f vco n1 m n2 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 104 ? 2007-2012 microchip technology inc. 8.2 oscillator resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 8.2.1 key resources ? section 7. ?oscillator? (ds70186) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 105 dspic33fj32mc202/204 and dspic33fj16mc304 8.3 oscillator control registers register 8-1: osccon: os cillator control register (1,3) u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y ? cosc<2:0> ? nosc<2:0> (2) bit 15 bit 8 r/w-0 r/w-0 r-0 u-0 r/c-0 u-0 r/w-0 r/w-0 clklock iolock lock ?cf ? lposcen oswen bit 7 bit 0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc<2:0>: current oscillator selection bits (read-only) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with pll 000 = fast rc oscillator (frc) bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc<2:0>: new oscillator selection bits (2) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with pll 000 = fast rc oscillator (frc) bit 7 clklock: clock lock enable bit if clock switching is enabled and fscm is disabled, (fosc dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 106 ? 2007-2012 microchip technology inc. bit 3 cf: clock fail detect bit (read/clear by application) 1 = fscm has detect ed clock failure 0 = fscm has not dete cted clock failure bit 2 unimplemented: read as ? 0 ? bit 1 lposcen: secondary (lp) oscillator enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = request oscillator switch to se lection specified by nosc<2:0> bits 0 = oscillator switch is complete register 8-1: osccon: os cillator control register (1,3) (continued) note 1: writes to this register require an unlock sequence. refer to section 7. ?oscillator? (ds70186) in the ?dspic33f/pic24h family reference manual? for details. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the applic ation must switch to frc mode as a transition clock source between the two pll modes. 3: this register is reset only on a power-on reset (por). ? 2007-2012 microchip technology inc. ds70283k-page 107 dspic33fj32mc202/204 and dspic33fj16mc304 register 8-2: clkdiv: clock divisor register (2) r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 roi doze<2:0> dozen (1) frcdiv<2:0> bit 15 bit 8 r/w-0 r/w-1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pllpost<1:0> ? pllpre<4:0> bit 7 bit 0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts will clear the dozen bit and the proce ssor clock/peripheral clock ratio is set to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze<2:0>: processor clock reduction select bits 111 = f cy /128 110 = f cy /64 101 = f cy /32 100 = f cy /16 011 = f cy /8 (default) 010 = f cy /4 001 = f cy /2 000 = f cy /1 bit 11 dozen: doze mode enable bit (1) 1 = doze<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = processor clock/peripheral clock ratio forced to 1:1 bit 10-8 frcdiv<2:0>: internal fast rc osci llator postscaler bits 111 = frc divide by 256 110 = frc divide by 64 101 = frc divide by 32 100 = frc divide by 16 011 = frc divide by 8 010 = frc divide by 4 001 = frc divide by 2 000 = frc divide by 1 (default) bit 7-6 pllpost<1:0>: pll vco output divider select bits (also denoted as ?n2?, pll postscaler) 11 = output/8 10 = reserved 01 = output/4 (default) 00 = output/2 bit 5 unimplemented: read as ? 0 ? bit 4-0 pllpre<4:0>: pll phase detector input divider bits (also denoted as ?n1?, pll prescaler) 00000 = input/2 (default) 00001 = input/3 ? ? ? 11111 = input/33 note 1: this bit is cleared when the roi bit is set and an interrupt occurs. 2: this register is reset only on a power-on reset (por). dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 108 ? 2007-2012 microchip technology inc. register 8-3: pllfbd: pll feedback divisor register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?plldiv<8> bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 plldiv<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8-0 plldiv<8:0>: pll feedback divisor bits (also denoted as ?m?, pll multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 ? ? ? 000110000 = 50 (default) ? ? ? 111111111 = 513 note 1: this register is reset only on a power-on reset (por). ? 2007-2012 microchip technology inc. ds70283k-page 109 dspic33fj32mc202/204 and dspic33fj16mc304 register 8-4: osctun: frc os cillator tuning register (2) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun<5:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frc oscillator tuning bits (1) 011111 = center frequency + 11.625% (8.23 mhz) 011110 = center frequency + 11.25% (8.20 mhz) ? ? ? 000001 = center frequency + 0.375% (7.40 mhz) 000000 = center frequency (7.37 mhz nominal) 111111 = center frequency -0.375% (7.345 mhz) ? ? ? 100001 = center frequency -11.625% (6.52 mhz) 100000 = center frequency -12% (6.49 mhz) note 1: osctun functionality has been provided to help cu stomers compensate for temperature effects on the frc frequency over a wide range of temperatures. the t uning step size is an approximation and is neither characterized nor tested. 2: this register is reset only on a power-on reset (por). dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 110 ? 2007-2012 microchip technology inc. 8.4 clock switching operation applications are free to s witch among any of the four clock sources (primary, lp, frc and lprc) under software control at any time . to limit the possible side effects of this flexibility, dspic33fj32mc202/204 and dspic33fj16mc304 devices have a safeguard lock built into the switch process. 8.4.1 enabling clock switching to enable clock switching, the fcksm1 configuration bit in the configuration register must be programmed to ? 0 ?. (refer to section 21.1 ?configuration bits? for further details.) if the fcksm1 configuration bit is unprogrammed (? 1 ?), the clock switching function and fail-safe clock monitor function are disabled. this is the default setting. the nosc control bits (osccon<10:8>) do not control the clock selecti on when clock switching is disabled. however, the cosc bits (osccon<14:12>) reflect the clock source selected by the fnosc configuration bits. the oswen control bit (osccon<0>) has no effect when clock switching is disabled. it is held at ? 0 ? at all times. 8.4.2 oscillato r switching sequence performing a clock switch requires this basic sequence: 1. if desired, read the cosc bits (osccon<14:12>) to determine the current oscillator source. 2. perform the unlock sequence to allow a write to the osccon register high byte. 3. write the appropriate value to the nosc control bits (osccon<10:8>) for the new oscillator source. 4. perform the unlock sequence to allow a write to the osccon register low byte. 5. set the oswen bit (osccon<0>) to initiate the oscillator switch. once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. the clock switching hardware compares the cosc status bits with the new value of the nosc control bits. if they are the same, the clock switch is a redundant operation. in this case, the oswen bit is cleared automatically and the clock switch is aborted. 2. if a valid clock switch has been initiated, the lock (osccon<5>) and the cf (osccon<3>) status bits are cleared. 3. the new oscillator is turned on by the hardware if it is not currently running. if a crystal oscillator must be turned on, the hardware waits until the oscillator start-up timer (ost) expires. if the new source is using the pll, the hardware waits until a pll lock is detected (lock = 1 ). 4. the hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 5. the hardware clears the oswen bit to indicate a successful clock transition. in addition, the nosc bit values are transferred to the cosc status bits. 6. the old clock source is turned off at this time, with the exception of lprc (if wdt or fscm are enabled) or lp (if lposcen remains set). 8.5 fail-safe clock monitor (fscm) the fail-safe clock monitor (fscm) allows the device to continue to operate even in the event of an oscillator failure. the fscm function is enabled by programming. if the fscm function is enabled, the lprc internal oscillator runs at all times (except during sleep mode) and is not subject to control by the watchdog timer. in the event of an oscillator failure, the fscm generates a clock failure tr ap event and switches the system clock over to the frc oscillator. then the application program can either attempt to restart the oscillator or execute a controlled shutdown. the trap can be treated as a warm reset by simply loading the reset address into the os cillator fail trap vector. if the pll multiplier is us ed to scale the system clock, the internal frc is also multiplied by the same factor on clock failure. es sentially, the device switches to frc with pll on a clock failure. note: primary oscillator mode has three different submodes (xt, hs and ec), which are determined by the poscmd<1:0> configuration bits. while an application can switch to and from primary oscillator mode in software, it cannot switch among the different primary submodes without reprogramming the device. note 1: the processor continues to execute code throughout the clock switching sequence. timing-sensitive code should not be executed during this time. 2: direct clock switches between any pri- mary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direc- tion. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes. 3: refer to section 7. ?oscillator? (ds70186) in the ?dspic33f/pic24h family reference manual? for details. ? 2007-2012 microchip technology inc. ds70283k-page 111 dspic33fj32mc202/204 and dspic33fj16mc304 9.0 power-saving features the dspic33fj32mc202/204 and dspic33fj16mc304 devices provide the ability to manage power consumption by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. dspic33fj32mc202/204 and dspic33fj16mc304 devices can manage power consumption in four different ways: ? clock frequency ? instruction-based sleep and idle modes ? software-controlled doze mode ? selective peripheral control in software combinations of these methods can be used to selec- tively tailor an application?s power consumption while still maintaining critical application features, such as timing-sensitive communications. 9.1 clock frequency and clock switching dspic33fj32mc202/204 and dspic33fj16mc304 devices allow a wide range of clock frequencies to be selected under appl ication control. if the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the nosc bits (osccon<10:8>). the process of changing a syst em clock during operation, as well as limitations to the process, are discussed in more detail in section 8.0 ?oscillator configuration? . 9.2 instruction-based power-saving modes dspic33fj32mc202/204 and dspic33fj16mc304 devices have two special power-saving modes that are entered through the execution of a special pwrsav instruction. sleep mode stop s clock operation and halts all code execution. idle mode halts the cpu and code execution, but allows peri pheral modules to continue operation. the assembler syntax of the pwrsav instruction is shown in example 9-1 . sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to wake-up. 9.2.1 sleep mode the following occur in sleep mode: ? the system clock source is shut down. if an on-chip oscillator is used, it is turned off. ? the device current consumption is reduced to a minimum, provided that no i/o pin is sourcing current. ? the fail-safe clock monitor does not operate, since the system clock source is disabled. ? the lprc clock continues to run in sleep mode if the wdt is enabled. ? the wdt, if enabled, is automatically cleared prior to entering sleep mode. ? some device features or peripherals may continue to operate. this includes items such as the input change notification on the i/o ports, or peripherals that use an external clock input. ? any peripheral that r equires the system clock source for its operation is disabled. the device will wake-up from sleep mode on any of the these events: ? any interrupt source that is individually enabled ? any form of device reset ? a wdt time-out on wake-up from sleep mode, the processor restarts with the same clock source th at was active when sleep mode was entered. example 9-1: pwrsav instruction syntax note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 9. ?watchdog timer and power-saving modes? (ds70196) the ? dspic33f/pic24h family reference manual ?, which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: sleep_mode and idle_mode are con- stants defined in the assembler include file for the selected device. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 112 ? 2007-2012 microchip technology inc. 9.2.2 idle mode the following occur in idle mode: ? the cpu stops executing instructions. ? the wdt is automatically cleared. ? the system clock sour ce remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 9.4 ?peripheral module disable? ). ? if the wdt or fscm is enabled, the lprc also remains active. the device will wake from idle mode on any of these events: ? any interrupt that is individually enabled ? any device reset ? a wdt time-out on wake-up from idle mode, the clock is reapplied to the cpu and instruction execution will begin (2-4 cycles later), starting with the instruction following the pwrsav instruction, or the first instruction in the isr. 9.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction is held off until entry into sleep or idle mode has completed. the device then wakes up from sleep or idle mode. 9.3 doze mode the preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. in some circumstances, this may not be practical. for example, it may be necessary for an application to maintain uninterrupted synchronous co mmunication, even while it is doing nothing else. reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock continues to operate from th e same source and at the same speed. peripheral modules continue to be clocked at the same speed, while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze<2:0> bits (clkdiv<14:12>). there are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. programs can use doze mode to selectively reduce power consumption in event-driven applications. this allows clock-sensitive func tions, such as synchronous communications, to continue without interruption while the cpu idles, waiting for something to invoke an interrupt routine. an automatic return to full-speed cpu operation on interrupts can be enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. for example, suppose the device is operating at 20 mips and the can module has been configured for 500 kbps based on this device operating speed. if the device is placed in doze mode with a clock frequency ratio of 1:4, the can module continues to communicate at the required bit rate of 500 kbps, but the cpu now starts executing instructions at a frequency of 5 mips. 9.4 peripheral module disable the peripheral module disable registers (pmd) provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabl ed using the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled, so writes to those registers will have no effect and read values will be invalid. a peripheral module is enabled only if both the associated bit in the pmd register is cleared and the peripheral is supported by the specific dspic ? dsc variant. if the peripheral is present in the device, it is enabled in the pmd register by default. note: if a pmd bit is set, the corresponding module is disabled after a delay of one instruction cycle. simila rly, if a pmd bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). ? 2007-2012 microchip technology inc. ds70283k-page 113 dspic33fj32mc202/204 and dspic33fj16mc304 9.5 power-saving resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 9.5.1 key resources ? section 9. ?watchdog timer and power-saving modes? (ds70196) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 114 ? 2007-2012 microchip technology inc. 9.6 power-saving control registers register 9-1: pmd1: peripheral mo dule disable control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 ? ? t3md t2md t1md qeimd pwm1md ? bit 15 bit 8 r/w-0 u-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 i2c1md ?u1md ?spi1md ? ?ad1md (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 t3md: timer3 module disable bit 1 = timer3 module is disabled 0 = timer3 module is enabled bit 12 t2md: timer2 module disable bit 1 = timer2 module is disabled 0 = timer2 module is enabled bit 11 t1md: timer1 module disable bit 1 = timer1 module is disabled 0 = timer1 module is enabled bit 10 qeimd: qei module disable bit 1 = qei module is disabled 0 = qei module is enabled bit 9 pwm1md: pwm1 module disable bit 1 = pwm1 module is disabled 0 = pwm1 module is enabled bit 8 unimplemented: read as ? 0 ? bit 7 i2c1md: i2c1 module disable bit 1 = i2c1 module is disabled 0 = i2c1 module is enabled bit 6 unimplemented: read as ? 0 ? bit 5 u1md: uart1 module disable bit 1 = uart1 module is disabled 0 = uart1 module is enabled bit 4 unimplemented: read as ? 0 ? bit 3 spi1md: spi1 module disable bit 1 = spi1 module is disabled 0 = spi1 module is enabled bit 2-1 unimplemented: read as ? 0 ? bit 0 ad1md: adc1 module disable bit (1) 1 = adc1 module is disabled 0 = adc1 module is enabled note 1: pcfgx bits have no effect if the adc module is disabled by setting this bit. in this case, all port pins multiplexed with anx will be in digital mode. ? 2007-2012 microchip technology inc. ds70283k-page 115 dspic33fj32mc202/204 and dspic33fj16mc304 register 9-2: pmd2: peripheral mo dule disable control register 2 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ic8md ic7md ? ? ? ?ic2mdic1md bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ?oc2mdoc1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ic8md: input capture 8 module disable bit 1 = input capture 8 module is disabled 0 = input capture 8 module is enabled bit 14 ic7md: input capture 2 module disable bit 1 = input capture 7 module is disabled 0 = input capture 7 module is enabled bit 13-10 unimplemented: read as ? 0 ? bit 9 ic2md: input capture 2 module disable bit 1 = input capture 2 module is disabled 0 = input capture 2 module is enabled bit 8 ic1md: input capture 1 module disable bit 1 = input capture 1 module is disabled 0 = input capture 1 module is enabled bit 7-2 unimplemented: read as ? 0 ? bit 1 oc2md: output compare 2 module disable bit 1 = output compare 2 module is disabled 0 = output compare 2 module is enabled bit 0 oc1md: output compare 1 module disable bit 1 = output compare 1 module is disabled 0 = output compare 1 module is enabled dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 116 ? 2007-2012 microchip technology inc. register 9-3: pmd3: peripheral mo dule disable control register 3 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 ? ? ?pwm2md ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4 pwm2md: pwm2 module disable bit 1 = pwm2 module is disabled 0 = pwm2 module is enabled bit 3-0 unimplemented: read as ? 0 ? ? 2007-2012 microchip technology inc. ds70283k-page 117 dspic33fj32mc202/204 and dspic33fj16mc304 10.0 i/o ports all of the device pins (except v dd , v ss , mclr and osc1/clki) are shared am ong the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 10.1 parallel i/o (pio) ports generally a parallel i/o port that shares a pin with a peripheral is subservient to the peripheral. the peripheral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripher al or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents ?loop through?, in which a port?s digital output can drive the input of a peripheral that shares the same pin. figure 10-1 shows how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin can be read, but the output driver for the parallel port bit is disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. all port pins have three registers directly associated with their operation as digital i/o. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx) read the latch. writes to the latch write t he latch. reads from the port (portx) read the port pins, while writes to the port pins write the latch. any bit and its associated data and control registers that are not valid for a particular device will be disabled. that means the corresponding latx and trisx registers and the port pin will read as zeros. when a pin is shared wit h another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other compet ing source of outputs. figure 10-1: block diagram of a typical shared port structure note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 devices. it is not intended to be a comprehensive refer- ence source. to complement the infor- mation in this data sheet, refer to section 10. ?i/o ports? (ds70193) of the ?dspic33f/pic24h family reference manual? , which is available on microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read port read tris 1 0 1 0 wr tris peripheral output data output enable peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read lat dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 118 ? 2007-2012 microchip technology inc. 10.2 open-drain configuration in addition to the port, lat and tris registers for data control, some port pins can also be individually configured for either digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits con- figures the corresponding pin to act as an open-drain output. the open-drain feature a llows the generation of outputs higher than v dd (e.g., 5v) on any desired 5v tolerant pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. see the ? pin diagrams ? section for the available pins and their functionality. 10.3 configuring analog port pins the ad1pcfg and tris registers control the opera- tion of the analog-to-digital (a/d) port pins. the port pins that are to function as analog inputs must have their corresponding tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the ad1pcfgl register has a default value of 0x0000; therefore, all pins that s hare anx functions are analog (not digital) by default. when the port register is read, all pins configured as analog input channels will read as cleared (a low level). pins configured as digital inputs will not convert an analog input. analog levels on any pin defined as a dig- ital input (including the anx pins) can cause the input buffer to consume current that exceeds the device specifications. 10.4 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be an nop . examples are shown in example 10-1 and example 10-2 . this also applies to port bit operations, such as bset portb , # rb0 , which are single cycle read-modify-write. all port bit operations, such as mov portb, w0 or bset portb , # rbx , read the pin and not the latch. 10.5 input change notification the input change notification function of the i/o ports allows the dspic33fj32mc202/204 and dspic33fj16mc304 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. this feature can detect input change-of-states even in sleep mode, when the clocks are disabled. depending on the device pin count, up to 31 external signals (cnx pin) can be selected (enabled) for generating an interrupt request on a change-of-state. four control registers are associated with the cn mod- ule. the cnen1 and cnen2 registers contain the interrupt enable control bits for each of the cn input pins. setting any of these bits enables a cn interrupt for the corresponding pins. each cn pin also has a weak pull-up connected to it. the pull-ups act as a current source connected to the pin, and eliminate the need for external resistors when push-button or keypad de vices are connected. the pull-ups are enabled separately using the cnpu1 and cnpu2 registers, which contain the control bits for each of the cn pins. sett ing any of the control bits enables the weak pull-ups for the corresponding pins. example 10-1: port write/read example example 10-2: port bit operations note: pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. mov 0xff00, w0 ; configure portb<15:8> as inputs mov w0, trisbb ; and portb<7:0> as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction incorrect: bset portb, #rb1 ;set portb ? 2007-2012 microchip technology inc. ds70283k-page 119 dspic33fj32mc202/204 and dspic33fj16mc304 10.6 peripheral pin select peripheral pin select configuration enables peripheral set selection and placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their ent ire application, rather than trimming the application to fit the device. the peripheral pin select configuration feature operates over a fixed subset of digital i/o pins. programmers can independently map the input and/or output of most digital peripherals to any one of these i/o pins. peripheral pin select is performed in software, and generally does not require the device to be reprogrammed. hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping, once it has been established. 10.6.1 available pins the peripheral pin select feature is used with a range of up to 26 pins. the number of available pins depends on the particular device and its pin count. pins that support the peripheral pin se lect feature include the designation ?rpn? in their full pin designation, where ?rp? designates a remappable peripheral and ?n? is the remappable pin number. 10.6.2 controlling peripheral pin select peripheral pin select features are controlled through two sets of special functi on registers: one to map peripheral inputs, and one to map outputs. because they are separately controlled, a particular peripheral?s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an in put or output is being mapped. 10.6.2.1 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral. a control register associated with a peripheral dictates the pin it will be mapped to. the rpinrx registers are used to configure peripheral input mapping (see register 10-1 through register 10-13 ). each register contains sets of 5-bit fields, with each set associated with one of the remappable peripherals. programming a given peripheral?s bit field with an appropriate 5-bit value maps the rpn pin with that value to that peripheral. for any given device, the valid range of values for any bit field corresponds to the maximum number of peripheral pin selections supported by the device. figure 10-2 illustrates remappable pin selection for u1rx input. figure 10-2: remappable mux input for u1rx note: for input mapping only, the peripheral pin select (pps) functio nality does not have priority over the trisx settings. there- fore, when configuring the rpn pin for input, the corresponding bit in the trisx register must also be configured for input (i.e., set to ? 1 ?). rp0 rp1 rp2 rp25 0 25 1 2 u1rx input u1rxr<4:0> to peripheral dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 120 ? 2007-2012 microchip technology inc. table 10-1: selectable input sources (maps input to function) (1) input name function name register configuration bits external interrupt 1 int1 rpinr0 int1r<4:0> external interrupt 2 int2 rpinr1 int2r<4:0> timer2 external clock t2ck rpinr3 t2ckr<4:0> timer3 external clock t3ck rpinr3 t3ckr<4:0> input capture 1 ic1 rpinr7 ic1r<4:0> input capture 2 ic2 rpinr7 ic2r<4:0> input capture 7 ic7 rpinr10 ic7r<4:0> input capture 8 ic8 rpinr10 ic8r<4:0> output compare fault a ocfa rpinr11 ocfar<4:0> pwm1 fault flta1 rpinr12 flta1r<4:0> pwm2 fault flta2 rpinr13 flta2r<4:0> qei1 phase a qea rpinr14 qea1r<4:0> qei1 phase b qeb rpinr14 qeb1r<4:0> qei1 index indx rpinr15 indx1r<4:0> uart1 receive u1rx rpinr18 u1rxr<4:0> uart1 clear to send u1cts rpinr18 u1ctsr<4:0> spi1 data input sdi1 rpinr20 sdi1r<4:0> spi1 clock input sck1 rpinr20 sck1r<4:0> spi1 slave select input ss1 rpinr21 ss1r<4:0> note 1: unless otherwise noted, all inputs use the schmitt input buffers. ? 2007-2012 microchip technology inc. ds70283k-page 121 dspic33fj32mc202/204 and dspic33fj16mc304 10.6.2.2 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rporx registers are used to control output mapping. like the rpinrx registers, each register contains sets of 5-bit fields, with each set associated with one rpn pin (see register 10-14 through register 10-26 ). the value of the bit field corresponds to one of the periph- erals, and that peripheral?s output is mapped to the pin (see table 10-2 and figure 10-3 ). the list of peripherals for output mapping also includes a null value of 00000 because of the mapping tech- nique. this permits any given pin to remain uncon- nected from the output of any of the pin selectable peripherals. figure 10-3: multiplexing of remappable output for rpn table 10-2: output selection for remappable pin (rpn) 0 26 3 rpnr<4:0> default u1tx output enable u1rts output enable 4 updn output enable 19 oc2 output enable 0 26 3 default u1tx output u1rts output 4 updn output 19 oc2 output output enable output data rpn function rpnr<4:0> output name null 00000 rpn tied to default port pin u1tx 00011 rpn tied to uart1 transmit u1rts 00100 rpn tied to uart1 ready to send sdo1 00111 rpn tied to spi1 data output sck1out 01000 rpn tied to spi1 clock output ss1out 01001 rpn tied to spi1 slave select output oc1 10010 rpn tied to output compare 1 oc2 10011 rpn tied to output compare 2 updn 11010 rpn tied to qei direction (updn) status dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 122 ? 2007-2012 microchip technology inc. 10.6.3 controllin g configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dspic33f devices include three features to prevent alterations to the peripheral map: ? control register lock sequence ? continuous state monitoring ? configuration bit pin select lock 10.6.3.1 control register lock under normal operation, writ es to the rpinrx and rporx registers are not allowed. attempted writes appear to execute normally, but the contents of the registers remain unchanged. to change these registers, they must be unlocked in hardware. the register lock is contro lled by the iolock bit (osccon<6>). sett ing iolock prevents writes to the control registers; clearin g iolock allows writes. to set or clear iolock, a specific command sequence must be executed: 1. write 0x46 to osccon<7:0>. 2. write 0x57 to osccon<7:0>. 3. clear (or set) iolock as a single operation. unlike the similar sequence with the oscillator?s lock bit, iolock remains in one state until changed. this allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. 10.6.3.2 continuous state monitoring in addition to being protect ed from direct writes, the contents of the rpinrx and rporx registers are constantly monitored in hardware by shadow registers. if an unexpected change in any of the registers occurs (such as cell disturbances caused by esd or other external events), a configuration mismatch reset will be triggered. 10.6.3.3 configuration bit pin select lock as an additional level of safety, the device can be configured to prevent more than one write session to the rpinrx and rporx registers. the iol1way (fosc ? 2007-2012 microchip technology inc. ds70283k-page 123 dspic33fj32mc202/204 and dspic33fj16mc304 10.7 i/o helpful tips 1. in some cases, certain pins as defined in table 24-9: ?dc characteristics: i/o pin input speci- fications? under ?injection current?, have internal protection diodes to v dd and v ss . the term ?injection current? is al so referred to as ?clamp current?. on designated pins, with sufficient exter- nal current limiting precautions by the user, i/o pin input voltages are allowed to be greater or less than the data sheet absolute maximum ratings with nominal v dd with respect to the v ss and v dd supplies. note that when the user application for- ward biases either of the high or low side internal input clamp diodes, that the resulting current being injected into the device that is clamped internally by the v dd and v ss power rails, may affect the adc accuracy by four to six counts. 2. i/o pins that are shared with any analog input pin, (i.e., anx), are always analog pins by default after any reset. consequently, any pin(s) configured as an analog input pin, automatically disables the dig- ital input pin buffer. as such, any attempt to read a digital input pin will always return a ? 0 ? regardless of the digital logic level on the pin if the analog pin is configured. to use a pin as a digital i/o pin on a shared anx pin, the user application needs to con- figure the analog pin configuration registers in the adc module, (i.e., adxpcfgl, ad1pcfgh), by setting the appropriate bit that corresponds to that i/o port pin to a ? 1 ?. on devices with more than one adc, both analog pin conf igurations for both adc modules must be configured as a digital i/o pin for that pin to function as a digital i/o pin. 3. most i/o pins have multiple functions. referring to the device pin diagrams in the data sheet, the pri- orities of the functions allocated to any pins are indicated by reading the pin name from left-to-right. the left most function name takes pre- cedence over any function to its right in the naming convention. for exampl e: an16/t2ck/t7ck/rc1. this indicates that an16 is the highest priority in this example and will super sede all other functions to its right in the list. those other functions to its right, even if enabled, w ould not work as long as any other function to its left was enabled. this rule applies to all of the functions listed for a given pin. 4. each cn pin has a configurable internal weak pull-up resistor. the pull-ups act as a current source connected to the pin, and eliminates the need for external resistors in certain applica- tions. the internal pull-up is to ~(v dd -0.8) not v dd . this is still above the minimum v ih of cmos and ttl devices. 5. when driving leds directly, the i/o pin can source or sink more current than what is specified in the v oh /i oh and v ol /i ol dc characteristic specifica- tion. the respective i oh and i ol current rating only applies to maintaining the corresponding output at or above the v oh and at or below the v ol levels. however, for leds unlike digital inputs of an exter- nally connected device, they are not governed by the same minimum v ih /v il levels. an i/o pin out- put can safely sink or source any current less than that listed in the absolute maximum rating section of the data sheet. for example: v oh = 2.4v @ i oh = -8 ma and v dd = 3.3v the maximum output current sourced by any 8 ma i/o pin = 12 ma. led source current < 12 ma is technically permitted. refer to the v oh /i oh graphs in section 24.0 ?electrical characteristics? for additional information. 10.8 i/o resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 10.8.1 key resources ? section 10. ?i/o ports? (ds70193) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: although it is not possible to use a digital input pin when its analog function is enabled, it is possible to use the digital i/o output function, tris x = 0x0, while the analog function is also enabled. however, this is not recommended, particularly if the analog input is connected to an external analog voltage source, which would cre- ate signal contention between the analog signal and the output pin driver. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 124 ? 2007-2012 microchip technology inc. 10.9 peripheral pin select registers the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices implement 21 registers for remappable peripheral configuration: ? input remappable peripheral registers (13) ? output remappable peripheral registers (8) note: input and output register values can only be changed if osccon[iolock] = 0 . see section 10.6.3.1 ?control register lock? for a specific command sequence. register 10-1: rpinr0: peripheral pin select input register 0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?int1r<4:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 int1r<4:0>: assign external interrupt 1 (intr1) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-0 unimplemented: read as ? 0 ? ? 2007-2012 microchip technology inc. ds70283k-page 125 dspic33fj32mc202/204 and dspic33fj16mc304 register 10-2: rpinr1: peripheral pin select input register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?int2r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 int2r<4:0>: assign external interrupt 2 (intr2) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 126 ? 2007-2012 microchip technology inc. register 10-3: rpinr3: peripheral pin select input register 3 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?t3ckr<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?t2ckr<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 t3ckr<4:0>: assign timer3 external clock (t3ck) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 t2ckr<4:0>: assign timer2 external clock (t2ck) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 ? 2007-2012 microchip technology inc. ds70283k-page 127 dspic33fj32mc202/204 and dspic33fj16mc304 register 10-4: rpinr7: peripheral pin select input register 7 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic2r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 ic2r<4:0>: assign input capture 2 (ic2) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 ic1r<4:0>: assign input capture 1 (ic1) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 128 ? 2007-2012 microchip technology inc. register 10-5: rpinr10: peripheral pin select input register 10 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic8r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ic7r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 ic8r<4:0>: assign input capture 8 (ic8) to the corresponding pin rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 ic7r<4:0>: assign input capture 7 (ic7) to the corresponding pin rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 ? 2007-2012 microchip technology inc. ds70283k-page 129 dspic33fj32mc202/204 and dspic33fj16mc304 register 10-6: rpinr11: peripheral pin select input register 11 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?ocfar<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ocfar<4:0>: assign output capture a (ocfa) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 register 10-7: rpinr12: periphera l pin select input register 12 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?flta1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 flta1r<4:0>: assign pwm1 fault (flta1 ) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 130 ? 2007-2012 microchip technology inc. register 10-8: rpinr13: peripheral pin select input register 13 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?flta2r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 flta2r<4:0>: assign pwm2 fault (flta2 ) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 ? 2007-2012 microchip technology inc. ds70283k-page 131 dspic33fj32mc202/204 and dspic33fj16mc304 register 10-9: rpinr14: periphera l pin select output register 14 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?qeb1r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?qea1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 qeb1r<4:0>: assign b (qeb) to the corresponding pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 qea1r<4:0>: assign a(qea) to the corresponding pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 132 ? 2007-2012 microchip technology inc. register 10-10: rpinr15: periphe ral pin select input register 15 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? indx1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 indx1r<4:0>: assign qei index (indx) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 ? 2007-2012 microchip technology inc. ds70283k-page 133 dspic33fj32mc202/204 and dspic33fj16mc304 register 10-11: rpinr18: periphe ral pin select input register 18 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? u1ctsr<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?u1rxr<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 u1ctsr<4:0>: assign uart1 clear to send (u1cts ) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 u1rxr<4:0>: assign uart1 receive (u1rx) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 134 ? 2007-2012 microchip technology inc. register 10-12: rpinr20: periphe ral pin select input register 20 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?sck1r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ?sdi1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 sck1r<4:0>: assign spi1 clock input (sck1in) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 sdi1r<4:0>: assign spi1 data input (sdi1) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 ? 2007-2012 microchip technology inc. ds70283k-page 135 dspic33fj32mc202/204 and dspic33fj16mc304 register 10-13: rpinr21: peripheral pin select input register 21 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ss1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as ? 0 ? bit 4-0 ss1r<4:0>: assign spi1 slave select input (ss1in) to the corresponding rpn pin bits 11111 = input tied v ss 11001 = input tied to rp25 . . . 00001 = input tied to rp1 00000 = input tied to rp0 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 136 ? 2007-2012 microchip technology inc. register 10-14: rpor0: peripheral pin select output register 0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp1r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp0r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp1r<4:0>: peripheral output function is assigned to rp1 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp0r<4:0>: peripheral output function is assigned to rp0 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) register 10-15: rpor1: peripheral pin select output register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp3r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp2r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp3r<4:0>: peripheral output function is assigned to rp3 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp2r<4:0>: peripheral output function is assigned to rp2 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) ? 2007-2012 microchip technology inc. ds70283k-page 137 dspic33fj32mc202/204 and dspic33fj16mc304 register 10-16: rpor2: peripheral pin select output register 2 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp5r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp4r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp5r<4:0>: peripheral output function is assigned to rp5 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp4r<4:0>: peripheral output function is assigned to rp4 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) register 10-17: rpor3: peripheral pin select output register 3 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp7r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp6r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp7r<4:0>: peripheral output function is assigned to rp7 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp6r<4:0>: peripheral output function is assigned to rp6 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 138 ? 2007-2012 microchip technology inc. register 10-18: rpor4: peripheral pin select output register 4 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp9r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp8r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp9r<4:0>: peripheral output function is assigned to rp9 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp8r<4:0>: peripheral output function is assigned to rp8 output pin bits (see ta b l e 1 0 - 2 for peripheral function numbers) register 10-19: rpor5: peripheral pin select output register 5 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ?rp11r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp10r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp11r<4:0>: peripheral output function is assigned to rp11 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp10r<4:0>: peripheral output function is a ssigned to rp10 output pin bits (see table 10-2 for peripheral function numbers) ? 2007-2012 microchip technology inc. ds70283k-page 139 dspic33fj32mc202/204 and dspic33fj16mc304 register 10-20: rpor6: peripheral pin select output register 6 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp13r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp12r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp13r<4:0>: peripheral output function is assi gned to rp13 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp12r<4:0>: peripheral output function is a ssigned to rp12 output pin bits (see table 10-2 for peripheral function numbers) register 10-21: rpor7: peripheral pin select output register 7 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp15r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp14r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp15r<4:0>: peripheral output function is assi gned to rp15 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp14r<4:0>: peripheral output function is a ssigned to rp14 output pin bits (see table 10-2 for peripheral function numbers) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 140 ? 2007-2012 microchip technology inc. register 10-22: rpor8: peripheral pin select output register 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp17r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp16r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp17r<4:0>: peripheral output function is assi gned to rp17 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp16r<4:0>: peripheral output function is a ssigned to rp16 output pin bits (see table 10-2 for peripheral function numbers) register 10-23: rpor9: peripheral pin select output register 9 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp19r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp18r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp19r<4:0>: peripheral output function is assi gned to rp19 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp18r<4:0>: peripheral output function is a ssigned to rp18 output pin bits (see table 10-2 for peripheral function numbers) ? 2007-2012 microchip technology inc. ds70283k-page 141 dspic33fj32mc202/204 and dspic33fj16mc304 register 10-24: rpor10: periphera l pin select output register 10 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp21r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp20r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp21r<4:0>: peripheral output function is assi gned to rp21 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp20r<4:0>: peripheral output function is a ssigned to rp20 output pin bits (see table 10-2 for peripheral function numbers) register 10-25: rpor11: periphera l pin select output register 11 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp23r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp22r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp23r<4:0>: peripheral output function is assi gned to rp23 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp22r<4:0>: peripheral output function is a ssigned to rp22 output pin bits (see table 10-2 for peripheral function numbers) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 142 ? 2007-2012 microchip technology inc. register 10-26: rpor12: periphera l pin select output register 12 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp25r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? rp24r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 rp25r<4:0>: peripheral output function is assi gned to rp25 output pin bits (see table 10-2 for peripheral function numbers) bit 7-5 unimplemented: read as ? 0 ? bit 4-0 rp24r<4:0>: peripheral output function is a ssigned to rp24 output pin bits (see table 10-2 for peripheral function numbers) ? 2007-2012 microchip technology inc. ds70283k-page 143 dspic33fj32mc202/204 and dspic33fj16mc304 11.0 timer1 the timer1 module is a 16- bit timer, which can serve as the time counter for the real-time clock, or operate as a free-running interval timer/counter. timer1 can operate in three modes: ? 16-bit timer ? 16-bit synchronous counter ? 16-bit asynchronous counter timer1 also supports these features: ? timer gate operation ? selectable prescaler settings ? timer operation during cpu idle and sleep modes ? interrupt on 16-bit period register match or falling edge of external gate signal figure 11-1 presents a block diagram of the 16-bit timer module. to configure timer1 for operation: 1. set the ton bit (= 1 ) in the t1con register. 2. select the timer prescaler ratio using the tckps<1:0> bits in the t1con register. 3. set the clock and gating modes using the tcs and tgate bits in the t1con register. 4. set or clear the tsync bit in t1con to select synchronous or asynchronous operation. 5. load the timer period value into the pr1 register. 6. if interrupts are required, set the interrupt enable bit, t1ie. use the priority bits, t1ip<2:0>, to set the interrupt priority. figure 11-1: 16-bit time r1 module block diagram note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 11. ?timers? (ds70205) of the dspic33f/pic24h family reference manual , which is available from the micro- chip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. ton sosci sosco/ pr1 set t1if equal comparator tmr1 reset soscen 1 0 tsync q qd ck tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 t1ck tcs 1x 01 tgate 00 sync gate sync dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 144 ? 2007-2012 microchip technology inc. 11.1 timer resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 11.1.1 key resources ? section 11. ?timers? (ds70205) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 145 dspic33fj32mc202/204 and dspic33fj16mc304 11.2 timer1 control register register 11-1: t1con: timer1 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 ? tgate tckps<1:0> ?tsynctcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer1 gated time accumulation enable bit when t c s = 1 : this bit is ignored. when t c s = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0> timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as ? 0 ? bit 2 tsync: timer1 external clock input synchronization select bit when tcs = 1 : 1 = synchronize external clock input 0 = do not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit 1 = external clock from pin t1ck (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as ? 0 ? dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 146 ? 2007-2012 microchip technology inc. notes: ? 2007-2012 microchip technology inc. ds70283k-page 147 dspic33fj32mc202/204 and dspic33fj16mc304 12.0 timer2/3 feature the timer2/3 feature has three 2-bit timers that can also be configured as two independent 16-bit timers with selectable operating modes. as a 32-bit timer, the timer2/3 feature permits operation in three modes: ? two independent 16-bit timers (e.g., timer2 and timer3) with all 16-bit operating modes (except asynchronous counter mode) ? single 32-bit timer (timer2/3) ? single 32-bit synchronous counter (timer2/3) the timer2/3 feature also supports: ? timer gate operation ? selectable prescaler settings ? timer operation during idle and sleep modes ? interrupt on a 32-bit period register match ? time base for input capt ure and output compare modules (timer2 and timer3 only) ? adc1 event trigger (timer2/3 only) individually, all eight of the 16-bit timers can function as synchronous timers or counters. they also offer the features listed above, except for the event trigger. the operating modes and enabled features are determined by setting the appropriate bit(s) in the t2con, t3con registers. t2con registers are shown in generic form in register 12-1 . t3con registers are shown in register 12-2 . for 32-bit timer/counter opera tion, timer2 is the least significant word (lsw), and timer3 is the most significant word (msw) of the 32-bit timers. 12.1 32-bit operation to configure the timer2/3 feature timers for 32-bit operation: 1. set the t32 control bit. 2. select the prescaler ratio for timer2 using the tckps<1:0> bits. 3. set the clock and gating modes using the corresponding tcs and tgate bits. 4. load the timer period value. pr3 contains the most significant word of the value, while pr2 contains the least significant word. 5. if interrupts are required, set the interrupt enable bit, t3ie. use the priority bits, t3ip<2:0>, to set the interrupt priority. while timer2 controls the timer, the interrupt appears as a timer3 interrupt. 6. set the corresponding ton bit. the timer value at any point is stored in the register pair, tmr3:tmr2, which always contains the most sig- nificant word of the count, while tmr2 contains the least significant word. 12.2 16-bit operation to configure any of the timers for individual 16-bit operation: 1. clear the t32 bit corresponding to that timer. 2. select the timer prescaler ratio using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. load the timer period value into the prx register. 5. if interrupts are required, set the interrupt enable bit, txie. use the priority bits, txip<2:0>, to set the interrupt priority. 6. set the ton bit. note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 11. ?timers? (ds70205) of the ?dspic33f/pic24h fa mily reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: for 32-bit operation, t3con control bits are ignored. only t2con control bits are used for setup and control. timer2 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is generated with the timer3 interrupt flags. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 148 ? 2007-2012 microchip technology inc. figure 12-1: timer2/3 (32-bit) block diagram (1) figure 12-2: timer2 (16-bit) block diagram set t3if equal comparator pr3 pr2 reset lsb msb note 1: the 32-bit timer control bit, t32, must be set for 32-bit time r/counter operation. all control bits are respective to the t2con register. 2: the adc event trigger is available only on timer2/3. data bus<15:0> tmr3hld read tmr2 write tmr2 16 16 16 q q d ck tgate 0 1 ton tckps<1:0> 2 t cy tcs 1x 01 tgate 00 t2ck adc event trigger (2) gate sync prescaler 1, 8, 64, 256 sync tmr3 tmr2 16 ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs tgate t2ck pr2 set t2if equal comparator tmr2 reset q qd ck tgate 1 0 gate sync 1x 01 00 sync ? 2007-2012 microchip technology inc. ds70283k-page 149 dspic33fj32mc202/204 and dspic33fj16mc304 12.3 timer2/3 control registers register 12-1: t2con control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 ? tgate tckps<1:0> t32 ?tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer2 on bit when t32 = 1 : 1 = starts 32-bit timer2/3 0 = stops 32-bit timer2/3 when t32 = 0 : 1 = starts 16-bit timer2 0 = stops 16-bit timer2 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer2 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0>: timer2 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 t32: 32-bit timer mode select bit 1 = timer2 and timer3 form a single 32-bit timer 0 = timer2 and timer3 act as two 16-bit timers bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timer2 clock source select bit 1 = external clock from pin t2ck (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as ? 0 ? dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 150 ? 2007-2012 microchip technology inc. register 12-2: t3con control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton (2) ?tsidl (1) ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 ? tgate (2) tckps<1:0> (2) ? ?tcs (2) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer3 on bit (2) 1 = starts 16-bit timer3 0 = stops 16-bit timer3 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit (1) 1 = discontinue timer operation when device enters idle mode 0 = continue timer operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timer3 gated time accumulation enable bit (2) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0>: timer3 input clock prescale select bits (2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 unimplemented: read as ? 0 ? bit 1 tcs: timer3 clock source select bit (2) 1 = external clock from t3ck pin 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: when 32-bit timer operation is enabled (t32 = 1 ) in the timer control regist er (t2con<3>), the tsidl bit must be cleared to operate th e 32-bit timer in idle mode. 2: when the 32-bit timer operation is enabled (t32 = 1 ) in the timer control regist er (t2con<3>), these bits have no effect. ? 2007-2012 microchip technology inc. ds70283k-page 151 dspic33fj32mc202/204 and dspic33fj16mc304 13.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the dspic33fj32mc202/204 and dspic33fj16mc304 devices support up to eight input capture channels. the input capture module captures the 16-bit value of the selected time base register when an event occurs at the icx pin. the events that cause a capture event are listed below in three categories: 1. simple capture event modes: - capture timer value on every falling edge of input at icx pin - capture timer value on every rising edge of input at icx pin 2. capture timer value on every edge (rising and falling). 3. prescaler capture event modes: - capture timer value on every 4th rising edge of input at icx pin - capture timer value on every 16th rising edge of input at icx pin each input capture channel can select one of two 16-bit timers (timer2 or timer3) for the time base. the selected timer can use either an internal or external clock. other operational features include: ? device wake-up from capture pin during cpu sleep and idle modes ? interrupt on input capture event ? 4-word fifo buffer for capture values - interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled ? use of input capture to provide additional sources of external interrupts figure 13-1: input capture block diagram note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 12. ?input capture? (ds70198) of the ?dspic33f/pic24h family refer- ence manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. icxbuf icx pin icm<2:0> (icxcon<2:0>) mode select 3 10 set flag icxif (in ifsn register) tmr2 tmr3 edge detection logic 16 16 fifo r/w logic icxi<1:0> icov, icbne (icxcon<4:3>) icxcon interrupt logic system bus from 16-bit timers ictmr (icxcon<7>) fifo prescaler counter (1, 4, 16) and clock synchronizer note: an ?x? in a signal, register or bit nam e denotes the number of the capture channel. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 152 ? 2007-2012 microchip technology inc. 13.1 input capture resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 13.1.1 key resources ? section 12. ?input capture? (ds70198) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 153 dspic33fj32mc202/204 and dspic33fj16mc304 13.2 input capture registers register 13-1: icxcon: inpu t capture x control register u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?icsidl ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-0, hc r-0, hc r/w-0 r/w-0 r/w-0 ictmr ici<1:0> icov icbne icm<2:0> bit 7 bit 0 legend: hc = cleared in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 icsidl: input capture module stop in idle control bit 1 = input capture module will halt in cpu idle mode 0 = input capture module will continue to operate in cpu idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 ictmr: input capture timer select bits 1 = tmr2 contents are captured on capture event 0 = tmr3 contents are captured on capture event bit 6-5 ici<1:0>: select number of captures per interrupt bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture buffer empty status bit (read-only) 1 = input capture buffer is not empty, at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture mode select bits 111 = input capture functions as interrupt pin only when device is in sleep or idle mode (rising edge detect only, all other control bits are not applicable.) 110 = unused (module disabled) 101 = capture mode, every 16th rising edge 100 = capture mode, every 4th rising edge 011 = capture mode, every rising edge 010 = capture mode, every falling edge 001 = capture mode, every edge (rising and falling) (ici<1:0> bits do not control inte rrupt generation for this mode.) 000 = input capture module turned off dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 154 ? 2007-2012 microchip technology inc. notes: ? 2007-2012 microchip technology inc. ds70283k-page 155 dspic33fj32mc202/204 and dspic33fj16mc304 14.0 output compare the output compare module can select either timer2 or timer3 for its time ba se. the module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. the state of the output pi n changes when the timer value matches the compare register value. the output compare module generates either a single output pulse or a sequence of output pulses, by changing the state of the output pin on the compare match events. the output compare module can also generate interrupts on compare match events. the output compare module has multiple operating modes: ? active-low one-shot mode ? active-high one-shot mode ? toggle mode ? delayed one-shot mode ? continuous pulse mode ? pwm mode without fault protection ? pwm mode with fault protection figure 14-1: output compare module block diagram note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 13. ?output compare? (ds70209) of the ?dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. ocxr comparator output logic ocm<2:0> ocx set flag bit ocxif ocxrs mode select 3 0 1 octsel 0 1 16 16 ocfa tmr2 tmr2 q s r tmr3 tmr3 rollover rollover output logic output enable enable dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 156 ? 2007-2012 microchip technology inc. 14.1 output compare modes configure the output compare modes by setting the appropriate output compare mode bits (ocm<2:0>) in the output compare contro l register (ocxcon<2:0>). table 14-1 lists the different bit settings for the output compare modes. figure 14-2 illustrates the output compare operation for various modes. the user application must disable the associated timer when writing to the output compare control registers to avoid malfunctions. table 14-1: output compare modes figure 14-2: output compare operation note: see section 13. ?output compare? (ds70209) in the ?dspic33f/pic24h family reference manual? (ds70209) for ocxr and ocxrs register restrictions. ocm<2:0> mode ocx pin initial state ocx interrupt generation 000 module disabled controlled by gpio register ? 001 active-low one-shot 0 ocx rising edge 010 active-high one-shot 1 ocx falling edge 011 toggle mode current output is maintained ocx rising and falling edge 100 delayed one-shot 0 ocx falling edge 101 continuous pulse mode 0 ocx falling edge 110 pwm mode without fault protection 0 , if ocxr is zero 1 , if ocxr is non-zero no interrupt 111 pwm mode with fault protection 0 , if ocxr is zero 1 , if ocxr is non-zero ocfa falling edge for oc1 to oc4 ocxrs tmry ocxr timer is reset on period match continuous pulse mode (ocm = 101 ) pwm mode (ocm = 110 or 111 ) active-low one-shot (ocm = 001 ) active-high one-shot (ocm = 010 ) toggle mode (ocm = 011 ) delayed one-shot (ocm = 100 ) output compare mode enabled ? 2007-2012 microchip technology inc. ds70283k-page 157 dspic33fj32mc202/204 and dspic33fj16mc304 14.2 output compare resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 14.2.1 key resources ? section 13. ?output compare? (ds70209) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 158 ? 2007-2012 microchip technology inc. 14.3 output compare control register register 14-1: ocxcon: output compare x control register u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?ocsidl ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r-0 hc r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ocflt octsel ocm<2:0> bit 7 bit 0 legend: hc = cleared in hardware hs = set in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ocsidl: stop output compare in idle mode control bit 1 = output compare x will halt in cpu idle mode 0 = output compare x will continue to operate in cpu idle mode bit 12-5 unimplemented: read as ? 0 ? bit 4 ocflt: pwm fault condition status bit 1 = pwm fault condition has occurred (cleared in hardware only) 0 = no pwm fault condition has occurred (this bit is only used when ocm<2:0> = 111 .) bit 3 octsel: output compare timer select bit 1 = timer3 is the clock source for compare x 0 = timer2 is the clock source for compare x bit 2-0 ocm<2:0>: output compare mode select bits 111 = pwm mode on ocx, fault pin enabled 110 = pwm mode on ocx, fault pin disabled 101 = initialize ocx pin low, generate continuous output pulses on ocx pin 100 = initialize ocx pin low, generate single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initialize ocx pin high, compare event forces ocx pin low 001 = initialize ocx pin low, compare event forces ocx pin high 000 = output compare channel is disabled ? 2007-2012 microchip technology inc. ds70283k-page 159 dspic33fj32mc202/204 and dspic33fj16mc304 15.0 motor control pwm module the dspic33fj32mc202/204 and dspic33fj16mc304 device supports up to two dedicated pulse-width modulation (pwm) modules. the pwm1 module is a 6-channel pwm generator, and the pwm2 module is a 2-channel pwm generator. the pwm module has the following features: ? up to 16-bit resolution. ? on-the-fly pwm frequency changes. ? edge and center-aligned output modes. ? single pulse generation mode. ? interrupt support for asymmetrical updates in center-aligned mode. ? output override control for electrically commutative motor (ec m) operation or bldc. ? special event comparator for scheduling other peripheral events. ? fault pins to optionally drive each of the pwm output pins to a defined state. duty cycle updates configur able to be immediate or synchronized to the pwm time base. 15.1 pwm1: 6-channel pwm module this module simplifies the task of generating multiple synchronized pwm outputs. the following power and motion control applications are supported by the pwm module: ? 3-phase ac induction motor ? switched reluctance (sr) motor ? brushless dc (bldc) motor ? uninterruptible power supply (ups) this module contains th ree duty cycle generators, numbered 1 through 3. the module has six pwm output pins, numbered pwm1h1/pwm1l1 through pwm1h3/pwm1l3. the six i/o pins are grouped into high/low numbered pairs, deno ted by the suffix h or l, respectively. for complementary loads, the low pwm pins are always the complement of the corresponding high i/o pin. 15.2 pwm2: 2-channel pwm module this module provides an additional pair of complimentary pwm outputs that can be used for: ? independent pfc correction in a motor system ? induction cooking this module contains a duty cycle generator that provides two pwm outputs, numbered pwm2h1/pwm2l1. note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?motor control pwm? (ds70187) of the ?dspic33f/pic24h family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 160 ? 2007-2012 microchip technology inc. figure 15-1: 6-channel pwm module block diagram (pwm1) p1dc3 p1dc3 buffer pwm1con1 pwm1con2 p1tper comparator comparator channel 3 dead-time generator and p1tcon p1secmp comparator special event trigger p1ovdcon pwm enable and mode sfrs pwm manual control sfr channel 2 dead-time generator and channel 1 dead-time generator and pwm generator 2 pwm generator 1 pwm generator 3 sevtdir ptdir p1dtcon1 dead-time control sfrs pwm1l1 pwm1h1 pwm1l2 pwm1h2 note: details of pwm generator 1and pwm generator 2 are not shown for clarity. 16-bit data bus pwm1l3 pwm1h3 p1dtcon2 p1fltacon fault pin control sfrs pwm time base output driver block flta 1 override logic override logic override logic special event postscaler p1tper buffer p1tmr ? 2007-2012 microchip technology inc. ds70283k-page 161 dspic33fj32mc202/204 and dspic33fj16mc304 figure 15-2: 2-channel pwm module block diagram (pwm2) p2dc1 p2dc1buffer pwm2con1 pwm2con2 p2tper comparator comparator channel 1 dead-time generator and p2tcon p2secmp comparator special event trigger p2ovdcon pwm enable and mode sfrs pwm manual control sfr pwm generator 1 sevtdir ptdir p2dtcon1 dead-time control sfrs 16-bit data bus pwm2l1 pwm2h1 p2dtcon2 p2fltacon fault pin control sfrs pwm time base output driver block flta 2 override logic special event postscaler p2tper buffer p2tmr dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 162 ? 2007-2012 microchip technology inc. 15.3 motor control resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 15.3.1 key resources ? section 14. ?motor control pwm? (ds70187) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 163 dspic33fj32mc202/204 and dspic33fj16mc304 15.4 pwm control registers register 15-1: p x tcon: pwm time base control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 pten ?ptsidl ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptops<3:0> ptckps< 1:0> ptmod<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pten: pwm time base timer enable bit 1 = pwm time base is on 0 = pwm time base is off bit 14 unimplemented: read as ? 0 ? bit 13 ptsidl: pwm time base stop in idle mode bit 1 = pwm time base halts in cpu idle mode 0 = pwm time base runs in cpu idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7-4 ptops<3:0>: pwm time base output postscale select bits 1111 = 1:16 postscale ? ? ? 0001 = 1:2 postscale 0000 = 1:1 postscale bit 3-2 ptckps<1:0>: pwm time base input cl ock prescale select bits 11 = pwm time base input clock period is 64 t cy (1:64 prescale) 10 = pwm time base input clock period is 16 t cy (1:16 prescale) 01 = pwm time base input clock period is 4 t cy (1:4 prescale) 00 = pwm time base input clock period is t cy (1:1 prescale) bit 1-0 ptmod<1:0>: pwm time base mode select bits 11 = pwm time base operates in a continuous up/down count mode with interrupts for double pwm updates 10 = pwm time base operates in a continuous up/down count mode 01 = pwm time base operates in single pulse mode 00 = pwm time base operates in a free-running mode dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 164 ? 2007-2012 microchip technology inc. register 15-2: p x tmr: pwm timer count value register r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptdir ptmr<14:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptmr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ptdir: pwm time base count direction status bit (read-only) 1 = pwm time base is counting down 0 = pwm time base is counting up bit 14-0 ptmr <14:0>: pwm time base register count value bits register 15-3: p x tper: pwm time ba se period register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ptper<14:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ptper<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-0 ptper<14:0>: pwm time base period value bits ? 2007-2012 microchip technology inc. ds70283k-page 165 dspic33fj32mc202/204 and dspic33fj16mc304 register 15-4: p x secmp: special event compare register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sevtdir (1) sevtcmp<14:8> (2) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sevtcmp<7:0> (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 sevtdir: special event trigger time base direction bit (1) 1 = a special event trigger will occur when the pwm time base is counting downward 0 = a special event trigger will occur when the pwm time base is counting upward bit 14-0 sevtcmp<14:0>: special event compare value bits (2) note 1: sevtdir is compared with ptdir (p x tmr<15>) to generate the special event trigger. 2: pxsecmp<14:0> is compared with p x tmr<14:0> to generate the special event trigger. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 166 ? 2007-2012 microchip technology inc. register 15-5: pwmxcon1: pwm control register 1 (2) u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? pmod3 pmod2 pmod1 bit 15 bit 8 u-0 r/w-1 r/w-1 r/w-1 u-0 r/w-1 r/w-1 r/w-1 ? pen3h (1) pen2h (1) pen1h (1) ? pen3l (1) pen2l (1) pen1l (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 pmod3:pmod1: pwm i/o pair mode bits 1 = pwm i/o pin pair is in the independent pwm output mode 0 = pwm i/o pin pair is in the complementary output mode bit 7 unimplemented: read as ? 0 ? bit 6-4 pen3h:pen1h: pwmxh i/o enable bits (1) 1 = pwmxh pin is enabled for pwm output 0 = pwmxh pin disabled, i/o pin becomes general purpose i/o bit 3 unimplemented: read as ? 0 ? bit 2-0 pen3l:pen1l: pwmxl i/o enable bits (1) 1 = pwmxl pin is enabled for pwm output 0 = pwmxl pin disabled, i/o pin becomes general purpose i/o note 1: reset condition of the penxh and penxl bits depends on the value of the pwmpin configuration bit in the fpor configuration register. 2: pwm2 supports only 1 pwm i/o pin pair. ? 2007-2012 microchip technology inc. ds70283k-page 167 dspic33fj32mc202/204 and dspic33fj16mc304 register 15-6: pwm x con2: pwm control register 2 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? sevops<3:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? iue osync udis bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as ? 0 ? bit 11-8 sevops<3:0>: pwm special event trigger output postscale select bits 1111 = 1:16 postscale ? ? ? 0001 = 1:2 postscale 0000 = 1:1 postscale bit 7-3 unimplemented: read as ? 0 ? bit 2 iue: immediate update enable bit 1 = updates to the active pxdc registers are immediate 0 = updates to the active pxdc registers are synchronized to the pwm time base bit 1 osync: output override synchronization bit 1 = output overrides via the pxovdcon register are synchronized to the pwm time base 0 = output overrides via the px ovdcon register occur on next t cy boundary bit 0 udis: pwm update disable bit 1 = updates from duty cycle and period buffer registers are disabled 0 = updates from duty cycle and period buffer registers are enabled dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 168 ? 2007-2012 microchip technology inc. register 15-7: p x dtcon1: dead-time control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dtbps<1:0> dtb<5:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dtaps<1:0> dta<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 dtbps<1:0>: dead-time unit b prescale select bits 11 = clock period for dead-time unit b is 8 t cy 10 = clock period for dead-time unit b is 4 t cy 01 = clock period for dead-time unit b is 2 t cy 00 = clock period for dead-time unit b is t cy bit 13-8 dtb<5:0>: unsigned 6-bit dead-time value for dead-time unit b bits bit 7-6 dtaps<1:0>: dead-time unit a prescale select bits 11 = clock period for dead-time unit a is 8 t cy 10 = clock period for dead-time unit a is 4 t cy 01 = clock period for dead-time unit a is 2 t cy 00 = clock period for dead-time unit a is t cy bit 5-0 dta<5:0>: unsigned 6-bit dead-time value for dead-time unit a bits ? 2007-2012 microchip technology inc. ds70283k-page 169 dspic33fj32mc202/204 and dspic33fj16mc304 register 15-8: p x dtcon2: dead-time control register 2 (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dts3a dts3i dts2a dts2i dts1a dts1i bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 dts3a: dead-time select for pwm3 signal going active bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 4 dts3i: dead-time select for pwm3 signal going inactive bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 3 dts2a: dead-time select for pwm2 signal going active bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 2 dts2i: dead-time select for pwm2 signal going inactive bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 1 dts1a: dead-time select for pwm1 signal going active bit 1 = dead time provided from unit b 0 = dead time provided from unit a bit 0 dts1i: dead-time select for pwm1 signal going inactive bit 1 = dead time provided from unit b 0 = dead time provided from unit a note 1: pwm2 supports only 1 pwm i/o pin pair. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 170 ? 2007-2012 microchip technology inc. register 15-9: p x fltacon: fault a control register (1) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? faov3h faov3l faov2h faov2l faov1h faov1l bit 15 bit 8 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 fltam ? ? ? ? faen3 faen2 faen1 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 faovxh<3:1>:faovxl<3:1>: fault input a pwm override value bits 1 = the pwm output pin is driven acti ve on an external fault input event 0 = the pwm output pin is driven in active on an external fault input event bit 7 fltam: fault a mode bit 1 = the fault a input pin functions in the cycle-by-cycle mode 0 = the fault a input pin latches all control pins to the programmed states in pxfltacon<13:8> bit 6-3 unimplemented: read as ? 0 ? bit 2 faen3: fault input a enable bit 1 = pwmxh3/pwmxl3 pin pair is controlled by fault input a 0 = pwmxh3/pwmxl3 pin pair is not controlled by fault input a bit 1 faen2: fault input a enable bit 1 = pwmxh2/pwmxl2 pin pair is controlled by fault input a 0 = pwmxh2/pwmxl2 pin pair is not controlled by fault input a bit 0 faen1: fault input a enable bit 1 = pwmxh1/pwmxl1 pin pair is controlled by fault input a 0 = pwmxh1/pwmxl1 pin pair is not controlled by fault input a note 1: pwm2 supports only 1 pwm i/o pin pair. ? 2007-2012 microchip technology inc. ds70283k-page 171 dspic33fj32mc202/204 and dspic33fj16mc304 register 15-10: p x ovdcon: override control register (1) u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? povd3h povd3l povd2h povd2l povd1h povd1l bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? pout3h pout3l pout2h pout2l pout1h pout1l bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13-8 povdxh<3:1>:povdxl<3:1>: pwm output override bits 1 = output on pwmx i/o pin is controlled by the pwm generator 0 = output on pwmx i/o pin is controlled by the value in the corresponding poutxh:poutxl bit bit 7-6 unimplemented: read as ? 0 ? bit 5-0 poutxh<3:1>:poutxl<3:1>: pwm manual output bits 1 = pwmx i/o pin is driven active when th e corresponding povdxh:povdxl bit is cleared 0 = pwmx i/o pin is driven inactive when the corresponding povdxh:povdxl bit is cleared note 1: pwm2 supports only 1 pwm i/o pin pair. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 172 ? 2007-2012 microchip technology inc. register 15-11: p x dc1: pwm duty cycle register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc1<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc1<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pdc1<15:0>: pwm duty cycle 1 value bits register 15-12: p1dc2: pwm duty cycle register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc2<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc2<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pdc2<15:0>: pwm duty cycle 2 value bits register 15-13: p1dc3: pwm duty cycle register 3 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc3<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pdc3<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 pdc3<15:0>: pwm duty cycle 3 value bits ? 2007-2012 microchip technology inc. ds70283k-page 173 dspic33fj32mc202/204 and dspic33fj16mc304 16.0 quadrature encoder interface (qei) module this section describes the quadrature en coder inter- face (qei) module and associated operational modes. the qei module provides the interface to incremental encoders for obtaining mechanical position data. the operational features of the qei include: ? three input channels for two phase signals and index pulse ? 16-bit up/down position counter ? count direction status ? position measurement (x2 and x4) mode ? programmable digital noise filters on inputs ? alternate 16-bit timer/counter mode ? quadrature encoder interface interrupts these operating modes are determined by setting the appropriate bits, qeim<2:0> in (qeixcon<10:8>). figure 16-1 depicts the quadrature encoder interface block diagram. figure 16-1: quadrature encoder interface block diagram note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 15. ?quadrature encoder interface (qei)? (ds70208) of the ?dspic33f/pic24h family reference manual? , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. 16-bit up/down counter comparator/ max count register qeax indxx 0 1 up/down existing pin logic updnx 3 qebx qeim<2:0> mode select 3 (poscnt) (maxcnt) pcdout qeiif event flag reset equal 2 t cy 1 0 tqcs tqckps<1:0> 2 q q d ck tqgate qeim<2:0> 1 0 sleep input 0 1 updn_src qeixcon<11> zero detect synchronize det 1, 8, 64, 256 prescaler quadrature encoder interface logic programmable digital filter programmable digital filter programmable digital filter dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 174 ? 2007-2012 microchip technology inc. 16.1 ouadrature encoder interface resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 16.1.1 key resources ? section 15. ?quadrature encoder interface (qei)? (ds70208) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools 16.2 control and status registers the qei module has four user-accessible registers, accessible in either byte or word mode: ? control/status register (qeicon) ? allows control of the qei operation and status flags indicating the module state. ? digital filter control register (dfltcon) ? allows control of the digital input filter operation. ? position count register (poscnt) ? allows reading and writing of th e 16-bit position counter. ? maximum count register (maxcnt) ? holds a value that is compared to the poscnt counter in some operations. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 note: the poscnt register allows byte accesses. however, reading the register in byte mode can result in partially updated values in subsequent reads. either use word mode reads/writes, or ensure that the counter is not counting during byte operations. ? 2007-2012 microchip technology inc. ds70283k-page 175 dspic33fj32mc202/204 and dspic33fj16mc304 register 16-1: qeixcon: qei control register r/w-0 u-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 cnterr ? qeisidl index updn qeim<2:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 swpab pcdout tqgate tqckps<1:0> posres tqcs updn_src bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cnterr: count error status flag bit 1 = position count error has occurred 0 = no position count error has occurred note: cnterr flag only applies when qeim<2:0> = ? 110 ? or ? 100 ?. bit 14 unimplemented: read as ? 0 ? bit 13 qeisidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 index: index pin state status bit (read-only) 1 = index pin is high 0 = index pin is low bit 11 updn: position counter direction status bit 1 = position counter direction is positive (+) 0 = position counter direction is negative (-) (read-only bit when qeim<2:0> = ? 1xx ?) (read/write bit when qeim<2:0> = ? 001 ?) bit 10-8 qeim<2:0>: quadrature encoder interface mode select bits 111 = quadrature encoder interface enabled (x4 mode) with position co unter reset by match (maxcnt) 110 = quadrature encoder interface enabled (x4 mode) with index pulse reset of position counter 101 = quadrature encoder interface enabled (x2 mode) with position co unter reset by match (maxcnt) 100 = quadrature encoder interface enabled (x2 mode) with index pulse reset of position counter 011 = unused (module disabled) 010 = unused (module disabled) 001 = starts 16-bit timer 000 = quadrature encode r interface/timer off bit 7 swpab: phase a and phase b input swap select bit 1 = phase a and phase b inputs swapped 0 = phase a and phase b inputs not swapped bit 6 pcdout: position counter direction state output enable bit 1 = position counter direction status output enable (qei logic controls state of i/o pin) 0 = position counter direction status ou tput disabled (normal i/o pin operation) bit 5 tqgate: timer gated time a ccumulation enable bit 1 = timer gated time accumulation enabled 0 = timer gated time accumulation disabled dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 176 ? 2007-2012 microchip technology inc. bit 4-3 tqckps<1:0>: timer input clock pr escale select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value (prescaler utilized for 16-bit timer mode only) bit 2 posres: position counter reset enable bit 1 = index pulse resets position counter 0 = index pulse does not reset position counter note: bit applies only when qeim<2:0> = 100 or 110 . bit 1 tqcs: timer clock source select bit 1 = external clock from pin qea (on the rising edge) 0 = internal clock (tcy) bit 0 updn_src: position counter direction selection control bit 1 = qeb pin state defines position counter direction 0 = control/status bit, updn (qeicon<11>) , defines timer counter (poscnt) direction note: when configured for qei mode, control bit is a ?don?t care?. register 16-1: qeixcon: qei co ntrol register (continued) ? 2007-2012 microchip technology inc. ds70283k-page 177 dspic33fj32mc202/204 and dspic33fj16mc304 register 16-2: dfltxcon: digi tal filter control register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ?imv<1:0>ceid bit 15 bit 8 r/w-0 r/w-0 u-0 u-0 u-0 u-0 qeout qeck<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-9 imv<1:0>: index match value bits ? these bits allow the user application to specify the state of the qea and qeb input pins during an index pulse when the posxcnt register is to be reset. in 4x quadratu re count mode: imv1 = required state of phase b input signal for match on index pulse imv0 = required state of phase a input signal for match on index pulse in 2x quadratu re count mode: imv1 = selects phase input signal for index state match ( 0 = phase a, 1 = phase b) imv0 = required state of the selected phase input signal for match on index pulse bit 8 ceid: count error interrupt disable bit 1 = interrupts due to count errors are disabled 0 = interrupts due to count errors are enabled bit 7 qeout: qea/qeb/indx pin digital filter output enable bit 1 = digital filter outputs enabled 0 = digital filter outputs disabled (normal pin operation) bit 6-4 qeck<2:0>: qea/qeb/indx digital filt er clock divide select bits 111 = 1:256 clock divide 110 = 1:128 clock divide 101 = 1:64 clock divide 100 = 1:32 clock divide 011 = 1:16 clock divide 010 = 1:4 clock divide 001 = 1:2 clock divide 000 = 1:1 clock divide bit 3-0 unimplemented: read as ? 0 ? dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 178 ? 2007-2012 microchip technology inc. notes: ? 2007-2012 microchip technology inc. ds70283k-page 179 dspic33fj32mc202/204 and dspic33fj16mc304 17.0 serial peripheral interface (spi) the serial peripheral interface (spi) module is a syn- chronous serial interface useful for communicating with other peripheral or microc ontroller devices. these peripheral devices can be serial eeproms, shift regis- ters, display drivers, analog -to-digital converters, etc. the spi module is compatib le with spi and siop from motorola ? . each spi module consists of a 16-bit shift register, spixsr (where x = 1 or 2), used for shifting data in and out, and a buffer register, spixbuf. a control register, spixcon, configures the module. additionally, a status register, spixstat, indica tes status conditions. the serial interface consis ts of these four pins: ? sdix (serial data input) ? sdox (serial data output) ? sckx (shift clock input or output) ? ssx (active-low slave select) in master mode operation, sck is a clock output. in slave mode, it is a clock input. figure 17-1: spi module block diagram note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 18. ?serial peripheral interface (spi)? (ds70206) of the ?dspic33f/pic24h family reference manual? , which is available on the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. internal data bus sdix sdox ssx sckx spixsr bit 0 shift control edge select f cy primary 1:1/4/16/64 enable prescaler sync spixbuf control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0> spixcon1<4:2> master clock clock control secondary prescaler 1:1 to 1:8 spixrxb spixtxb dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 180 ? 2007-2012 microchip technology inc. 17.1 spi helpful tips 1. in frame mode, if there is a possibility that the master may not be initialized before the slave: a) if frmpol (spixcon2<13>) = 1 , use a pull-down resistor on ssx . b) if frmpol = 0 , use a pull-up resistor on ssx . 2. in non-framed 3-wire mode, (i.e., not using ssx from a master): a) if ckp (spixcon1<6>) = 1 , always place a pull-up resistor on ssx . b) if ckp = 0 , always place a pull-down resistor on ssx . 3. frmen (spixcon2<15>) = 1 and ssen (spixcon1<7>) = 1 are exclusive and invalid. in frame mode, sckx is continuous and the frame sync pulse is active on the ssx pin, which indicates the start of a data frame. 4. in master mode only, set the smp bit (spixcon1<9>) to a ? 1 ? for the fastest spi data rate possible. the smp bit can only be set at the same time or after the msten bit (spixcon1<5>) is set. 5. to avoid invalid slave read data to the master, the user?s master software must guarantee enough time for slave software to fill its write buf- fer before the user application initiates a master write/read cycle. it is always advisable to pre- load the spixbuf transmit register in advance of the next master transaction cycle. spixbuf is transferred to the spi shift register and is empty once the data transmission begins. 17.2 spi resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 17.2.1 key resources ? section 18. ?serial peripheral interface (spi)? (ds70206) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: this insures that the first frame transmission after initialization is not shifted or corrupted. note: this will insure that during power-up and initialization the master/slave will not lose sync due to an errant sck transition that would cause the slave to accumulate data shift errors for both transmit and receive appearing as corrupted data. note: not all third-party devices support frame mode timing. refer to the spi electrical characteristics for details. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 181 dspic33fj32mc202/204 and dspic33fj16mc304 17.3 spi control registers register 17-1: spixstat: spix status and control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 spien ? spisidl ? ? ? ? ? bit 15 bit 8 u-0 r/c-0 u-0 u-0 u-0 u-0 r-0 r-0 ? spirov ? ? ? ? spitbf spirbf bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 spien: spix enable bit 1 = enables module and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables module bit 14 unimplemented: read as ? 0 ? bit 13 spisidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 spirov: receive overflow flag bit 1 = a new byte/word is completely received and discarded. the user software has not read the previous data in the spixbuf register 0 = no overflow has occurred. bit 5-2 unimplemented: read as ? 0 ? bit 1 spitbf: spix transmit buffer full status bit 1 = transmit not yet started, spixtxb is full 0 = transmit started, spixtxb is empty automatically set in hardware when cpu writes spixbuf location, loading spixtxb. automatically cleared in hardware when spix modu le transfers data from spixtxb to spixsr. bit 0 spirbf: spix receive buffer full status bit 1 = receive complete, spixrxb is full 0 = receive is not comp lete, spixrxb is empty automatically set in hardware when spix transfers data from spixsr to spixrxb. automatically cleared in hardware when core reads spixbuf location, reading spixrxb. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 182 ? 2007-2012 microchip technology inc. register 17-2: spi x con1: spix control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dissck dissdo mode16 smp cke (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen (2) ckp msten spre<2:0> (3) ppre<1:0> (3) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 dissck: disable sckx pin bit (spi master modes only) 1 = internal spi clock is disabled, pin functions as i/o 0 = internal spi clock is enabled bit 11 dissdo: disable sdox pin bit 1 = sdox pin is not used by module; pin functions as i/o 0 = sdox pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spix data input sample phase bit master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode: smp must be cleared when spix is used in slave mode. bit 8 cke: spix clock edge select bit (1) 1 = serial output data changes on transition from active clock state to idle clock state (see bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (see bit 6) bit 7 ssen: slave select enable bit (slave mode) (2) 1 = ssx pin used for slave mode 0 = ssx pin not used by module. pin controlled by port function bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high le vel; active state is a low level 0 = idle state for clock is a low le vel; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 = slave mode note 1: the cke bit is not used in the framed spi modes. program this bit to ? 0 ? for the framed spi modes (frmen = 1 ). 2: this bit must be cleared when frmen = 1 . 3: do not set both primary and secondary prescalers to a value of 1:1. ? 2007-2012 microchip technology inc. ds70283k-page 183 dspic33fj32mc202/204 and dspic33fj16mc304 bit 4-2 spre<2:0>: secondary prescale bits (master mode) (3) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 ? ? ? 000 = secondary prescale 8:1 bit 1-0 ppre<1:0>: primary prescale bits (master mode) (3) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 17-2: spi x con1: spix control register 1 (continued) note 1: the cke bit is not used in the framed spi modes. program this bit to ? 0 ? for the framed spi modes (frmen = 1 ). 2: this bit must be cleared when frmen = 1 . 3: do not set both primary and secondary prescalers to a value of 1:1. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 184 ? 2007-2012 microchip technology inc. register 17-3: spixcon2: spix control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 frmen spifsd frmpol ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 ? ? ? ? ? ? frmdly ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 frmen: framed spix support bit 1 = framed spix support enabled (ssx pin used as frame sync pulse input/output) 0 = framed spix support disabled bit 14 spifsd: frame sync pulse direction control bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 frmpol: frame sync pulse polarity bit 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as ? 0 ? bit 1 frmdly: frame sync pulse edge select bit 1 = frame sync pulse coincides with first bit clock 0 = frame sync pulse precedes first bit clock bit 0 unimplemented: this bit must not be set to ? 1 ? by the user application ? 2007-2012 microchip technology inc. ds70283k-page 185 dspic33fj32mc202/204 and dspic33fj16mc304 18.0 inter-integrated circuit? (i 2 c?) the inter-integrated circuit (i 2 c) module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard, with a 16-bit interface. the i 2 c module has a 2-pin interface: ? the sclx pin is clock ? the sdax pin is data the i 2 c module offers the following key features: ?i 2 c interface supporting both master and slave modes of operation ?i 2 c slave mode supports 7-bit and 10-bit addressing ?i 2 c master mode supports 7-bit and 10-bit addressing ?i 2 c port allows bidirectional transfers between master and slaves ? serial clock synch ronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial trans fer (sclrel control) ?i 2 c supports multi-master operation, detects bus collision and arbitrates accordingly 18.1 operating modes the hardware fully implements all the master and slave functions of the i 2 c standard and fast mode specifications, as well as 7-bit and 10-bit addressing. the i 2 c module can operate either as a slave or a master on an i 2 c bus. the following types of i 2 c operation are supported: ?i 2 c slave operation with 7-bit addressing ?i 2 c slave operation with 10-bit addressing ?i 2 c master operation with 7- bit or 10-bit addressing for details about the communication sequence in each of these modes, refer to the ?dspic33f/pic24h family reference manual? . please see the microchip web site ( www.microchip.com ) for the latest dspic33f/pic24h family reference manual sections. note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 19. ?inter-integrated circuit? (i 2 c?)? (ds70195) of the ?dspic33f/pic24h family reference manual? , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 186 ? 2007-2012 microchip technology inc. figure 18-1: i 2 c? block diagram ( x = 1) internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control t cy /2 start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv ? 2007-2012 microchip technology inc. ds70283k-page 187 dspic33fj32mc202/204 and dspic33fj16mc304 18.2 i 2 c resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 18.2.1 key resources ? section 13. ?inter-integrated circuit? (i 2 c?)? (ds70195) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools 18.3 i 2 c registers i2cxcon and i2cxstat are control and status registers, respectively. the i2cxcon register is readable and writable. the lower six bits of i2cxstat are read-only. the remaining bits of the i2cstat are read/write: ? i2cxrsr is the shift register used for shifting data. ? i2cxrcv is the receive buffer and the register to which data bytes are written, or from which data bytes are read. ? i2cxtrn is the transmit register to which bytes are written during a transmit operation. ? the i2cxadd register holds the slave address. ? a status bit, add10, indicates 10-bit address mode. ? the i2cxbrg acts as the baud rate generator (brg) reload value. in receive operations, i2cxrsr and i2cxrcv together form a double-buffered receiver. when i2cxrsr receives a complete byte, it is transferred to i2cxrcv, and an interrupt pulse is generated. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 188 ? 2007-2012 microchip technology inc. 18.4 i 2 c control registers register 18-1: i2cxcon: i2cx control register r/w-0 u-0 r/w-0 r/w-1 hc r/w-0 r/w-0 r/w-0 r/w-0 i2cen ? i2csidl sclrel ipmien a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 hc r/w-0 hc r/w-0 hc r/w-0 hc r/w-0 hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hs = set in hardware hc = cleared in hardware -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 i2cen: i2cx enable bit 1 = enables the i2cx module and configures the sdax and sclx pins as serial port pins 0 = disables the i2cx module. all i 2 c pins are controlled by port functions bit 14 unimplemented: read as ? 0 ? bit 13 i2csidl: stop in idle mode bit 1 = discontinue module operation when device enters an idle mode 0 = continue module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = release sclx clock 0 = hold sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware clear at beginning of slave transmission. hard ware clear at end of slave reception. if stren = 0 : bit is r/s (i.e., software can only write ? 1 ? to release clock). hardware clear at beginning of slave transmission. bit 11 ipmien: intelligent peripheral management interface (ipmi) enable bit 1 = ipmi mode is enabled; all addresses acknowledged 0 = ipmi mode disabled bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control disabled 0 = slew rate control enabled bit 8 smen: smbus input levels bit 1 = enable i/o pin thresholds co mpliant with smbus specification 0 = disable smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enable interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with sclrel bit. 1 = enable software or receive clock stretching 0 = disable software or receive clock stretching ? 2007-2012 microchip technology inc. ds70283k-page 189 dspic33fj32mc202/204 and dspic33fj16mc304 bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that will be transmitted when the software initiates an acknowledge sequence. 1 = send nack during acknowledge 0 = send ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master, applicable during master receive) 1 = initiate acknowledge sequence on sdax an d sclx pins and transmit ackdt data bit. hardware clear at end of master acknowledge sequence 0 = acknowledge sequence not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware clear at end of eighth bit of master receive data byte 0 = receive sequence not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiate stop condition on sdax and sclx pi ns. hardware clear at end of master stop sequence 0 = stop condition not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiate repeated start condition on sdax and sclx pins. hardware clear at end of master repeated start sequence 0 = repeated start condition not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiate start condition on sdax and sclx pins . hardware clear at end of master start sequence 0 = start condition not in progress register 18-1: i2cxcon: i2cx control register (continued) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 190 ? 2007-2012 microchip technology inc. register 18-2: i2cxstat: i2cx status register r-0 hsc r-0 hsc u-0 u-0 u-0 r/c-0 hs r-0 hsc r-0 hsc ackstat trstat ? ? ? bcl gcstat add10 bit 15 bit 8 r/c-0 hs r/c-0 hs r-0 hsc r/c-0 hsc r/c-0 hsc r-0 hsc r-0 hsc r-0 hsc iwcol i2cov d_a p s r_w rbf tbf bit 7 bit 0 legend: u = unimplemented bit, read as ?0? c = clear only bit r = readable bit w = writable bit hs = set in hardware hsc = hardware set/cleared -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ackstat: acknowledge status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = nack received from slave 0 = ack received from slave hardware set or clear at end of slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware set at beginning of master transmission . hardware clear at end of slave acknowledge. bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detec ted during a master operation 0 = no collision hardware set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware set when address matches general call address. hardware clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware set at match of 2nd byte of matched 10 -bit address. hardware clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write the i2cx trn register failed because the i 2 c module is busy 0 = no collision hardware set at occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv re gister is still holding the previous byte 0 = no overflow hardware set at attempt to transfer i2cxrsr to i2cxrcv (cleared by software). bit 5 d_a: data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was device address hardware clear at device address match. hardware set by reception of slave byte. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware set or clear when start, repeated start or stop detected. ? 2007-2012 microchip technology inc. ds70283k-page 191 dspic33fj32mc202/204 and dspic33fj16mc304 bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 2 r_w: read/write information bit (when operating as i 2 c slave) 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave hardware set or clear after reception of i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty hardware set when i2cxrcv is written with received byte. hardware clear when software reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty hardware set when software writes i2cxtrn. hard ware clear at completion of data transmission. register 18-2: i2cxstat: i2cx status register (continued) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 192 ? 2007-2012 microchip technology inc. register 18-3: i2cxmsk: i2cx sl ave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? amsk9 amsk8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as ? 0 ? bit 9-0 amskx: mask for address bit x select bit 1 = enable masking for bit x of incoming message address; bit match not requ ired in this position 0 = disable masking for bit x; bit match required in this position ? 2007-2012 microchip technology inc. ds70283k-page 193 dspic33fj32mc202/204 and dspic33fj16mc304 19.0 universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules available in the dspic33fj32mc202/204 and dspic33fj16mc304 device family. the uart is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, lin, and rs-232 and rs-485 interfaces. the module also supports a hardware flow control option with the uxcts and uxrts pins and also includes an irda ? encoder and decoder. the primary features of the uart module are: ? full-duplex, 8-bit or 9-bit data transmission through the uxtx and uxrx pins ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware flow control option with uxcts and uxrts pins ? fully integrated baud rate generator with 16-bit prescaler ? baud rates ranging from 10 mbps to 38 bps at 40 mips ? 4-deep first-in first-out (fifo) transmit data buffer ? 4-deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for 9-bit mode with address detect (9th bit = 1 ) ? transmit and receive interrupts ? a separate interrupt for all uart error conditions ? loopback mode for diagnostic support ? support for sync and break characters ? support for automatic baud rate detection ?irda ? encoder and decoder logic ? 16x baud clock output for irda ? support a simplified block diagram of the uart module is shown in figure 19-1 . the uart module consists of these key hardware elements: ? baud rate generator ? asynchronous transmitter ? asynchronous receiver figure 19-1: uart simplified block diagram note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 17. ?uart? (ds70188) of the ?dspic33f/pic24h family reference manual? , which is available on the micro- chip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. uxrx hardware flow control uart receiver uart transmitter uxtx baud rate generator uxrts / bclk irda ? uxcts dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 194 ? 2007-2012 microchip technology inc. 19.1 uart helpful tips 1. in multi-node direct-connect uart networks, uart receive inputs react to the complementary logic level defined by the urxinv bit (uxmode<4>), which defines the idle state, the default of which is logic high, (i.e., urxinv = 0 ). because remote devices do not initialize at the same time , it is likely that one of the devices, because the rx line is floating, will trigger a start bit detection and will cause the first byte received after the device has been ini- tialized to be invalid. to avoid this situation, the user should use a pull-up or pull-down resistor on the rx pin depending on the value of the urxinv bit. a) if urxinv = 0 , use a pull-up resistor on the rx pin. b) if urxinv = 1 , use a pull-down resistor on the rx pin. 2. the first character received on a wake-up from sleep mode caused by activity on the uxrx pin of the uart module will be invalid. in sleep mode, peripheral clocks are disabled. by the time the oscillator system has restarted and stabilized from sleep mode, the baud rate bit sampling clock relative to the incoming uxrx bit timing is no longer synchronized, resulting in the first character being invalid. this is to be expected. 19.2 uart resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 19.2.1 key resources ? section 17. ?uart? (ds70188) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 195 dspic33fj32mc202/204 and dspic33fj16mc304 19.3 uart control registers register 19-1: uxmode: uart x mode register r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uarten (1) ? usidl iren (2) rtsmd ?uen<1:0> bit 15 bit 8 r/w-0 hc r/w-0 r/w-0, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud urxinv brgh pdsel<1:0> stsel bit 7 bit 0 legend: hc = hardware clearable r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit (1) 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by uen<1:0> 0 = uartx is disabled; all uartx pins are controll ed by port latches; uartx power consumption minimal bit 14 unimplemented: read as ? 0 ? bit 13 usidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 iren: irda ? encoder and decoder enable bit (2) 1 = irda encoder and decoder enabled 0 = irda encoder and decoder disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin in simplex mode 0 =uxrts pin in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen<1:0>: uartx pin enable bits 11 = uxtx, uxrx and bclk pins are enabled and used; uxcts pin controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /bclk pins controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx will continue to sample the uxrx pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = no wake-up enabled bit 6 lpback: uartx loopback mode select bit 1 = enable loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character ? requires reception of a sync field (55h) before other data; cleared in hardware upon completion 0 = baud rate measurement disabled or completed note 1: refer to section 17. ?uart? (ds70188) in the ?dspic33f/pic24h family reference manual? for information on enabling the uart module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 196 ? 2007-2012 microchip technology inc. bit 4 urxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? bit 3 brgh: high baud rate enable bit 1 = brg generates 4 clocks per bit period (4x baud clock, high-speed mode) 0 = brg generates 16 clocks per bit period (16x baud clock, standard mode) bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 19-1: uxmode: uart x mode register (continued) note 1: refer to section 17. ?uart? (ds70188) in the ?dspic33f/pic24h family reference manual? for information on enabling the uart module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). ? 2007-2012 microchip technology inc. ds70283k-page 197 dspic33fj32mc202/204 and dspic33fj16mc304 register 19-2: u x sta: uart x status and control register r/w-0 r/w-0 r/w-0 u-0 r/w-0 hc r/w-0 r-0 r-1 utxisel1 utxinv utxisel0 ? utxbrk utxen (1) utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/c-0 r-0 urxisel<1:0> adden ridle perr ferr oerr urxda bit 7 bit 0 legend: hc = hardware cleared c = clear only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15,13 utxisel<1:0>: transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register, and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted ou t of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to t he transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: transmit polarity inversion bit if iren = 0 : 1 = uxtx idle state is ? 0 ? 0 = uxtx idle state is ? 1 ? if iren = 1 : 1 =irda ? encoded uxtx idle state is ? 1 ? 0 =irda ? encoded uxtx idle state is ? 0 ? bit 12 unimplemented: read as ? 0 ? bit 11 utxbrk: transmit break bit 1 = send sync break on next transmission ? start bit, followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion 0 = sync break transmission disabled or completed bit 10 utxen: transmit enable bit (1) 1 = transmit enabled, uxtx pin controlled by uartx 0 = transmit disabled, any pending transmission is abo rted and buffer is reset. uxtx pin controlled by port bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at leas t one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is em pty and transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued bit 7-6 urxisel<1:0>: receive interrupt mode selection bits 11 = interrupt is set on uxrsr transfer making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on uxrsr transfer making the re ceive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is receiv ed and transferred from the uxrsr to the receive buffer. receive buffer has one or more characters note 1: refer to section 17. ?uart? (ds70188) in the ?dspic33f/pic24h family reference manual? for information on enabling the uart module for transmit operation. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 198 ? 2007-2012 microchip technology inc. bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode enabled. if 9-bit mode is not selected, this does not take effect 0 = address detect mode disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current ch aracter (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (read/clear only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed. clearing a previously set oerr bit ( 1 0 transition) will reset the receiver buffer and th e uxrsr to the empty state bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 19-2: u x sta: uart x status and control register (continued) note 1: refer to section 17. ?uart? (ds70188) in the ?dspic33f/pic24h family reference manual? for information on enabling the uart module for transmit operation. ? 2007-2012 microchip technology inc. ds70283k-page 199 dspic33fj32mc202/204 and dspic33fj16mc304 20.0 10-bit/12-bit analog-to-digital converter (adc) the dspic33fj32mc202/204 and dspic33fj16mc304 devices have up to nine analog-to-digital converter (adc) module input channels. the ad12b bit (ad1con1<10>) allows each of the adc modules to be config ured as either a 10-bit, 4 sample-and-hold adc (def ault configuration), or a 12-bit, 1 sample-and-hold adc. 20.1 key features the 10-bit adc configuration has the following key features: ? successive approximation (sar) conversion ? conversion speeds of up to 1.1 msps ? up to 9 analog input pins ? external voltage reference input pins ? simultaneous sampling of up to four analog input pins ? automatic channel scan mode ? selectable conversion trigger source ? selectable buffer fill modes ? four result alignment options (signed/unsigned, fractional/integer) ? operation during cpu sleep and idle modes ? 16-word conversion result buffer the 12-bit adc configurat ion supports all the above features, except: ? in the 12-bit configurati on, conversion speeds of up to 500 ksps are supported. ? there is only 1 sample-and-hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. depending on the particular device pinout, the adc can have up to nine analog input pins, designated an0 through an8. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs can be shared with other analog input pins. the actual number of analog input pins and external voltage reference input configuration will depend on the specific device. refer to the device data sheet for further details. a block diagram of the adc is shown in figure 20-1 . 20.2 adc initialization to configure the adc module: 1. select port pins as analog inputs (ad1pcfgh<15:0> or ad1pcfgl<15:0>). 2. select voltage reference source to match expected range on analog inputs (ad1con2<15:13>). 3. select the analog conversion clock to match the desired data rate with the processor clock (ad1con3<7:0>). 4. determine how many sample-and-hold chan- nels will be used (ad1con2<9:8> and ad1pcfgh<15:0> or ad1pcfgl<15:0>). 5. select the appropriate sample/conversion sequence (ad1con1<7:5> and ad1con3<12:8>). 6. select the way conversion results are presented in the buffer (ad1con1<9:8>). 7. turn on the adc module (ad1con1<15>). 8. configure adc interrupt (if required): a) clear the ad1if bit. b) select the adc interrupt priority. note 1: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 16. ?analog-to-digital converter (adc)? (ds70183) of the ?dspic33f/pic24h family reference manual? , which is available on the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for de vice-specific register and bit information. note: the adc module must be disabled before the ad12b bit can be modified. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 200 ? 2007-2012 microchip technology inc. figure 20-1: adc1 module block di agram for dspic33fj16mc304 and dspic33fj32mc204 devices sar adc s/h0 s/h1 adc1buf0 adc1buf1 adc1buf2 adc1buff adc1bufe an0 an8 an1 v refl ch0sb<4:0> ch0na ch0nb + - an0 an3 ch123sa v refl ch123sb ch123na ch123nb an6 + - s/h2 an1 an4 ch123sa v refl ch123sb ch123na ch123nb an7 + - s/h3 an2 an5 ch123sa v refl ch123sb ch123na ch123nb an8 + - ch0 ch0sa<4:0> channel scan cscna alternate input selection v refh v refl ch1 (2) ch2 (2) ch3 (2) note 1: v ref +, v ref - inputs can be multiplexed with other analog inputs. 2: channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. av dd av ss v ref - (1) v ref + (1) vcfg<2:0> ? 2007-2012 microchip technology inc. ds70283k-page 201 dspic33fj32mc202/204 and dspic33fj16mc304 figure 20-2: adc1 module block diagram for dspic33fj32mc202 device sar adc s/h0 s/h1 adc1buf0 adc1buf1 adc1buf2 adc1buff adc1bufe an0 an5 an1 v refl ch0sb<4:0> ch0na ch0nb + - an0 an3 ch123sa v refl ch123sb ch123na ch123nb + - s/h2 an1 an4 ch123sa v refl ch123sb ch123na ch123nb + - s/h3 an2 an5 ch123sa v refl ch123sb ch123na ch123nb + - ch1 (2) ch0 ch2 (2) ch3 (2) ch0sa<4:0> channel scan cscna alternate v ref + (1) av dd av ss v ref - (1) note 1: v ref +, v ref - inputs can be multiplexed with other analog inputs. 2: channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. input selection v refh v refl vcfg<2:0> dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 202 ? 2007-2012 microchip technology inc. figure 20-3: adc conversion clock period block diagram 20.3 adc helpful tips 1. the smpi<3:0> (ad1con2 <5:2>) control bits: a) determine when the adc interrupt flag is set and an interrupt is generated if enabled. b) when the cscna bit (ad1con2<10>) is set to ? 1 ?, determines when the adc analog scan channel list defined in the ad1cssl/ad1cssh registers starts over from the beginning. c) on devices without a dma peripheral, determines when adc result buffer pointer to adc1buf0-adc1buff, gets reset back to the beginning at adc1buf0. 2. on devices without a dma module, the adc has 16 result buffers. adc conversion results are stored sequentially in adc1buf0-adc1buff regardless of which analog inputs are being used subject to the smpi<3:0> bits (ad1con2<5:2>) and the condition described in 1c above. there is no relationship between the anx input being measured and which adc buffer (adc1buf0-adc1buff) that the conversion results will be placed in. 3. on devices with a dma module, the adc mod- ule has only 1 adc result buffer, (i.e., adc1buf0), per adc peripheral and the adc conversion result must be read either by the cpu or dma controller before the next adc conversion is complete to avoid overwriting the previous value. 4. the done bit (ad1con1<0>) is only cleared at the start of each conversion and is set at the completion of the conv ersion, but remains set indefinitely even through the next sample phase until the next conversion begins. if application code is monitoring the done bit in any kind of software loop, the user must consider this behavior because the cpu code execution is faster than the adc. as a result, in manual sam- ple mode, particularly where the users code is setting the samp bit (ad1con1<1>), the done bit should also be cleared by the user application just before setting the samp bit. 5. on devices with two adc modules, the adcxpcfg registers for both adc modules must be set to a logic ? 1 ? to configure a target i/o pin as a digital i/o pin. failure to do so means that any alternate digital input function will always see only a logic ? 0 ? as the digital input buffer is held in disable mode. 20.4 adc resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 20.4.1 key resources ? section 16. ?analog-to-digital converter (adc)? (ds70183) ? code samples ? application notes ? software libraries ? webinars ? all related dspic33f/pic24h family reference manuals sections ? development tools 0 1 adc internal rc clock (2) t osc (1) x 2 adc conversion clock multiplier 1, 2, 3, 4, 5,..., 64 ad1con3<15> t cy t ad 6 ad1con3<5:0> note 1: refer to figure 8-2 for the derivation of f osc when the pll is enabled. if the pll is not used, f osc is equal to the clock frequency. t osc = 1/f osc . 2: see the adc electrical characteri stics for the exact rc clock value. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en530334 ? 2007-2012 microchip technology inc. ds70283k-page 203 dspic33fj32mc202/204 and dspic33fj16mc304 20.5 adc control registers register 20-1: ad1con1: adc1 control register 1 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 adon ?adsidl ? ? ad12b form<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 hc,hs r/c-0 hc, hs ssrc<2:0> ? simsam asam samp done bit 7 bit 0 legend: hc = cleared by hardware hs = set by hardware c = clear only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adon: adc operating mode bit 1 = adc module is operating 0 = adc is off bit 14 unimplemented: read as ? 0 ? bit 13 adsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10 ad12b: 10-bit or 12-bit operation mode bit 1 = 12-bit, 1-channel adc operation 0 = 10-bit, 4-channel adc operation bit 9-8 form<1:0>: data output format bits for 10-bit operation: 11 = signed fractional (d out = sddd dddd dd00 0000 , where s = .not.d<9>) 10 = fractional (d out = dddd dddd dd00 0000 ) 01 = signed integer (d out = ssss sssd dddd dddd , where s = .not.d<9>) 00 = integer (d out = 0000 00dd dddd dddd ) for 12-bit operation: 11 = signed fractional (d out = sddd dddd dddd 0000 , where s = .not.d<11>) 10 = fractional (d out = dddd dddd dddd 0000 ) 01 = signed integer (d out = ssss sddd dddd dddd , where s = .not.d<11>) 00 = integer (d out = 0000 dddd dddd dddd ) bit 7-5 ssrc<2:0>: sample clock source select bits 111 = internal counter ends sampling a nd starts conversion (auto-convert) 110 = reserved 101 = motor control pwm2 interval ends sampling and starts conversion 100 = reserved 011 = motor control pwm1 interval ends sampling and starts conversion 010 = gp timer 3 compare ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing sample bit ends sampling and starts conversion bit 4 unimplemented: read as ? 0 ? bit 3 simsam: simultaneous sample select bit (applicable only when chps<1:0> = 01 or 1x ) when ad12b = 1 , simsam is: u-0, unimplemented, read as ? 0 ? 1 = samples ch0, ch1, ch2, ch3 simultaneously (when chps<1:0> = 1x ); or samples ch0 and ch1 simultaneously (when chps<1:0> = 01 ) 0 = samples multiple channels individually in sequence dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 204 ? 2007-2012 microchip technology inc. bit 2 asam: adc sample auto-start bit 1 = sampling begins immediately after last conversion. samp bit is auto-set 0 = sampling begins when samp bit is set bit 1 samp: adc sample enable bit 1 = adc sample-and-hold amplifiers are sampling 0 = adc sample-and-hold amplifiers are holding if asam = 0 , software can write ? 1 ? to begin sampling. automatically set by hardware if asam = 1 . if ssrc = 000 , software can write ? 0 ? to end sampling and start conversion. if ssrc 000 , automatically cleared by hardware to end sampling and start conversion. bit 0 done: adc conversion status bit 1 = adc conversion cycle is completed 0 = adc conversion not started or in progress automatically set by hardware when adc conversion is complete. software can write ? 0 ? to clear done status (software not allowed to write ? 1 ?). clearing this bit will not affect any operation in progress. automatically cleared by hard ware at start of a new conversion. register 20-1: ad1con1: adc1 control register 1 (continued) ? 2007-2012 microchip technology inc. ds70283k-page 205 dspic33fj32mc202/204 and dspic33fj16mc304 register 20-2: ad1con2: adc1 control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 vcfg<2:0> ? ? cscna chps<1:0> bit 15 bit 8 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs ? smpi<3:0> bufm alts bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 vcfg<2:0>: converter voltage reference configuration bits bit 12-11 unimplemented: read as ? 0 ? bit 10 cscna: scan input selections for ch0+ during sample a bit 1 = scan inputs 0 = do not scan inputs bit 9-8 chps<1:0>: select channels utilized bits when ad12b = 1 , chps<1:0> is: u-0, unimplemented, read as ? 0 ? 1x = converts ch0, ch1, ch2 and ch3 01 = converts ch0 and ch1 00 = converts ch0 bit 7 bufs: buffer fill status bit (valid only when bufm = 1 ) 1 = adc is currently filling second half of buffer, user should access data in the first half 0 = adc is currently filling first half of buffer, us er application should access data in the second half bit 6 unimplemented: read as ? 0 ? bit 5-2 smpi<3:0>: sample/convert sequences per interrupt selection bits 1111 = interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = interrupts at the completion of conversion for each 15th sample/convert sequence ? ? ? 0001 = interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = interrupts at the completion of conversion for each sample/convert sequence bit 1 bufm: buffer fill mode select bit 1 = starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt 0 = always starts filling buffer from the beginning bit 0 alts: alternate input sample mode select bit 1 = uses channel input selects for sample a on first sample and sample b on next sample 0 = always uses channel i nput selects for sample a adref+ adref- 000 a vdd a vss 001 external v ref +a vss 010 a vdd external v ref - 011 external v ref + external v ref - 1xx a vdd a vss dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 206 ? 2007-2012 microchip technology inc. register 20-3: ad1con3: adc1 control register 3 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc ? ? samc<4:0> (1) bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs<7:0> (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adrc: adc conversion clock source bit 1 = adc internal rc clock 0 = clock derived from system clock bit 14-13 unimplemented: read as ? 0 ? bit 12-8 samc<4:0>: auto sample time bits (1) 11111 = 31 t ad ? ? ? 00001 = 1 t ad 00000 = 0 t ad bit 7-0 adcs<7:0>: adc conversion clock select bits (2) 11111111 = reserved ? ? ? ? 01000000 = reserved 00111111 = t cy (adcs<7:0> + 1) = 64 t cy = t ad ? ? ? 00000010 = t cy (adcs<7:0> + 1) = 3 t cy = t ad 00000001 = t cy (adcs<7:0> + 1) = 2 t cy = t ad 00000000 = t cy (adcs<7:0> + 1) = 1 t cy = t ad note 1: this bit only used if ad1con1<7:5> (ssrc2:0) = 111 . 2: this bit is not used if ad1con3<15> (adrc) = 1 . ? 2007-2012 microchip technology inc. ds70283k-page 207 dspic33fj32mc202/204 and dspic33fj16mc304 register 20-4: ad1chs123: adc1 in put channel 1, 2, 3 select register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ch123nb<1:0> ch123sb bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? ch123na<1:0> ch123sa bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-9 ch123nb<1:0>: channel 1, 2, 3 negative i nput select for sample b bits dspic33fj32mc202 devices only: if ad12b = 1 : 11 = reserved 10 = reserved 01 = reserved 00 = reserved if ad12b = 0 : 11 = reserved 10 = reserved 01 = ch1, ch2, ch3 negative input is v ref - 00 = ch1, ch2, ch3 negative input is v ref - dspic33fj32mc204 and dspic33fj16mc304 devices only: if ad12b = 1 : 11 = reserved 10 = reserved 01 = reserved 00 = reserved if ad12b = 0 : 11 = reserved 10 = ch1 negative input is an6, ch2 negative input is an7, ch3 negative input is an8 01 = ch1, ch2, ch3 negative input is v ref - 00 = ch1, ch2, ch3 negative input is v ref - bit 8 ch123sb: channel 1, 2, 3 positive input select for sample b bit if ad12b = 1 : 1 = reserved 0 = reserved if ad12b = 0 : 1 = ch1 positive input is an3, ch2 positive input is an4, ch3 positive input is an5 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 bit 7-3 unimplemented: read as ? 0 ? dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 208 ? 2007-2012 microchip technology inc. bit 2-1 ch123na<1:0>: channel 1, 2, 3 negative i nput select for sample a bits dspic33fj32mc202 devices only: if ad12b = 1 : 11 = reserved 10 = reserved 01 = reserved 00 = reserved if ad12b = 0 : 11 = reserved 10 = reserved 01 = ch1, ch2, ch3 negative input is v ref - 00 = ch1, ch2, ch3 negative input is v ref - dspic33fj32mc204 and dspic33fj16mc304 devices only: if ad12b = 1 : 11 = reserved 10 = reserved 01 = reserved 00 = reserved if ad12b = 0 : 11 = reserved 10 = ch1 negative input is an6, ch2 negative input is an7, ch3 negative input is an8 01 = ch1, ch2, ch3 negative input is v ref - 00 = ch1, ch2, ch3 negative input is v ref - bit 0 ch123sa: channel 1, 2, 3 positive input select for sample a bit if ad12b = 1 : 1 = reserved 0 = reserved if ad12b = 0 : 1 = ch1 positive input is an3, ch2 positive input is an4, ch3 positive input is an5 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 register 20-4: ad1chs123: adc1 input channe l 1, 2, 3 select register (continued) ? 2007-2012 microchip technology inc. ds70283k-page 209 dspic33fj32mc202/204 and dspic33fj16mc304 register 20-5: ad1chs0: adc1 input channel 0 select register r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ? ? ch0sb<4:0> bit 15 bit 8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na ? ? ch0sa<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ch0nb: channel 0 negative input select for sample b bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v ref - bit 14-13 unimplemented: read as ? 0 ? bit 12-8 ch0sb<4:0>: channel 0 positive input select for sample b bits dspic33fj32mc204 and dspic33fj16mc304 devices only: 01000 = channel 0 positive input is an8 ? ? ? 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 dspic33fj32mc202 devices only: 00101 = channel 0 positive input is an5 ? ? ? 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0. bit 7 ch0na: channel 0 negative input select for sample a bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v ref - bit 6-5 unimplemented: read as ? 0 ? bit 4-0 ch0sa<4:0>: channel 0 positive input select for sample a bits dspic33fj32mc204 and dspic33fj16mc304 devices only: 01000 = channel 0 positive input is an8 ? ? ? 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 dspic33fj32mc202 devices only: 00101 = channel 0 positive input is an5 ? ? ? 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 210 ? 2007-2012 microchip technology inc. ,2 register 20-6: ad1cssl: adc1 in put scan select register low (1,2) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? css8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css7 css6 css5 css4 css3 css2 css1 css0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8-0 css<8:0>: adc input scan selection bits 1 = select anx for input scan 0 = skip anx for input scan note 1: on devices without 9 analog inputs, all ad1cssl bits can be selected by the user application. however, inputs selected for scan without a corresponding input on device converts v refl . 2: cssx = anx, where x = 0 through 8. register 20-7: ad1pcfgl: adc1 po rt configuration register low (1,2,3) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?pcfg8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8-0 pcfg<8:0>: adc port configuration control bits 1 = port pin in digital mode, port read inpu t enabled, adc input multiplexer connected to av ss 0 = port pin in analog mode, port read input disabled, adc samples pin voltage note 1: on devices without 9 analog inputs, all pcfg bits ar e r/w by user software. however, the pcfg bits are ignored on ports without a corresponding input on device. 2: pcfgx = anx, where x = 0 through 8. 3: the pcfgx bits have no effect if the adc module is disabled by setting adxmd bit in the pmdx register. in this case, all port pins multiplexed with anx will be in digital mode. ? 2007-2012 microchip technology inc. ds70283k-page 211 dspic33fj32mc202/204 and dspic33fj16mc304 21.0 special features dspic33fj32mc202/204 and dspic33fj16mc304 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. these are: ? flexible configuration ? watchdog timer (wdt) ? code protection and codeguard? security ? jtag boundary scan interface ? in-circuit serial programming? (icsp?) ? in-circuit emulation 21.1 configuration bits dspic33fj32mc202/204 and dspic33fj16mc304 devices provide nonvolatile memory implementation for device configuration bits. refer to section 25. ?device configuration? (ds70194) of the ?dspic33f/pic24h family reference manual? , for more information on this implementation. the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped starting at program memory location 0xf80000. the individual configuration bit descriptions for the configuration registers are shown in table 21-2 . note that address 0xf80000 is beyond the user program memory space. it belongs to the configuration memory space (0x800000-0xffffff), which can only be accessed using table reads and table writes. the device configuration register map is shown in table 21-1 . note: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 devices. it is not intended to be a comprehensive refer- ence source. to comp lement the informa- tion in this data sheet, refer to the ?dspic33f/pic24h family reference manual? . please see the microchip web site ( www.microchip.com ) for the latest dspic33f/pic24h family reference manual sections. table 21-1: device configuration register map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xf80000 fbs ? ? ? ? bss<2:0> bwrp 0xf80002 reserved ? ? ? ? ? ? ? ? 0xf80004 fgs ? ? ? ? ? gss<1:0> gwrp 0xf80006 foscsel ieso ? ? ?fnosc<2:0> 0xf80008 fosc fcksm<1:0> iol1way ? ? osciofnc poscmd<1:0> 0xf8000a fwdt fwdten windis ? wdtpre wdtpost<3:0> 0xf8000c fpor pwmpin hpol lpol alti2c ?fpwrt<2:0> 0xf8000e ficd reserved (1) jtagen ? ? ?ics<1:0> 0xf80010 fuid0 user unit id byte 0 0xf80012 fuid1 user unit id byte 1 0xf80014 fuid2 user unit id byte 2 0xf80016 fuid3 user unit id byte 3 legend: ? = unimplemented bit, read as ? 0 ?. note 1: these bits are reserved for use by development tools and must be programmed as ? 1 ?. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 212 ? 2007-2012 microchip technology inc. table 21-2: configuration bits description bit field register rtsp effect description bwrp fbs immediate boot segment program flash write protection 1 = boot segment can be written 0 = boot segment is write-protected bss<2:0> fbs immediate dspic33fj32mc202 and dspic33fj32mc204 devices only boot segment program flash code protection size x11 = no boot program flash segment boot space is 768 instruction words (except interrupt vectors) 110 = standard security; boot program flash segment ends at 0x0007fe 010 = high security; boot program flash segment ends at 0x0007fe boot space is 3840 instruction words (except interrupt vectors) 101 = standard security; boot program flash segment, ends at 0x001ffe 001 = high security; boot program flash segment ends at 0x001ffe boot space is 7936 instruction words (except interrupt vectors) 100 = standard security; boot program flash segment ends at 0x003ffe 000 = high security; boot program flash segment ends at 0x003ffe bss<2:0> fbs immediate dspic33fj16mc304 device only boot segment program flash code protection size x11 = no boot program flash segment boot space is 768 instruction words (except interrupt vectors) 110 = standard security; boot program flash segment ends at 0x0007fe 010 = high security; boot program flash segment ends at 0x0007fe boot space is 3840 instruction words (except interrupt vectors) 101 = standard security; boot program flash segment, ends at 0x001ffe 001 = high security; boot program flash segment ends at 0x001ffe boot space is 5376 instruction words (except interrupt vectors) 100 = standard security; boot program flash segment ends at 0x002bfe 000 = high security; boot program flash segment ends at 0x002bfe gss<1:0> fgs immediate general segment code-protect bit 11 = user program memory is not code-protected 10 = standard security 0x = high security gwrp fgs immediate general segment write-protect bit 1 = user program memory is not write-protected 0 = user program memory is write-protected ieso foscsel immediate two-speed o scillator start-up enable bit 1 = start-up device with frc, then aut omatically switch to the user-selected oscillator source when ready 0 = start-up device with user-selected oscillator source fnosc<2:0> foscsel if clock switch is enabled, rtsp effect is on any device reset; otherwise, immediate initial oscillator source selection bits 111 = internal fast rc (frc) oscillator with postscaler 110 = internal fast rc (frc) oscillator with divide-by-16 101 = lprc oscillator 100 = secondary (lp) oscillator 011 = primary (xt, hs, ec) oscillator with pll 010 = primary (xt, hs, ec) oscillator 001 = internal fast rc (frc) oscillator with pll 000 = frc oscillator ? 2007-2012 microchip technology inc. ds70283k-page 213 dspic33fj32mc202/204 and dspic33fj16mc304 fcksm<1:0> fosc immediate clock switching mode bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled iol1way fosc immediate peripheral pin select configuration 1 = allow only one reconfiguration 0 = allow multiple reconfigurations osciofnc fosc immediate osc2 pin function bit (except in xt and hs modes) 1 = osc2 is clock output 0 = osc2 is general purpose digital i/o pin poscmd<1:0> fosc immediate primary oscillator mode select bits 11 = primary oscillator disabled 10 = hs crystal oscillator mode 01 = xt crystal oscillator mode 00 = ec (external clock) mode fwdten fwdt immediate watchdog timer enable bit 1 = watchdog timer always enabled (lprc oscillator cannot be disabled. clearing the swdten bit in the rcon register will have no effect.) 0 = watchdog timer enabled/disabled by user software (lprc can be dis- abled by clearing the swdten bit in the rcon register) windis fwdt immediate watchdog timer window enable bit 1 = watchdog timer in non-window mode 0 = watchdog timer in window mode wdtpre fwdt immediate watchdog timer prescaler bit 1 = 1:128 0 = 1:32 wdtpost<3:0> fwdt immediate watchdog timer postscaler bits 1111 = 1:32,768 1110 = 1:16,384 ? ? ? 0001 = 1:2 0000 = 1:1 pwmpin fpor immediate motor control pwm module pin mode bit 1 = pwm module pins controlled by port register at device reset (tri-stated) 0 = pwm module pins controlled by pwm module at device reset (configured as output pins) table 21-2: configuration bits description (continued) bit field register rtsp effect description dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 214 ? 2007-2012 microchip technology inc. hpol fpor immediate motor contro l pwm high side polarity bit 1 = pwm module high side output pins have active-high output polarity 0 = pwm module high side output pins have active-low output polarity lpol fpor immediate motor control pwm low side polarity bit 1 = pwm module low side output pins have active-high output polarity 0 = pwm module low side output pins have active-low output polarity fpwrt<2:0> fpor immediate power-on reset timer value select bits 111 = pwrt = 128 ms 110 = pwrt = 64 ms 101 = pwrt = 32 ms 100 = pwrt = 16 ms 011 = pwrt = 8 ms 010 = pwrt = 4 ms 001 = pwrt = 2 ms 000 = pwrt = disabled alti2c fpor immediate alternate i 2 c? pins 1 = i 2 c mapped to sda1/scl1 pins 0 = i 2 c mapped to asda1/ascl1 pins jtagen ficd immediate jtag enable bit 1 = jtag enabled 0 = jtag disabled ics<1:0> ficd immediate icd communication channel select bits 11 = communicate on pgec1 and pged1 10 = communicate on pgec2 and pged2 01 = communicate on pgec3 and pged3 00 = reserved, do not use table 21-2: configuration bits description (continued) bit field register rtsp effect description ? 2007-2012 microchip technology inc. ds70283k-page 215 dspic33fj32mc202/204 and dspic33fj16mc304 21.2 on-chip voltage regulator the dspic33fj32mc202/204 and dspic33fj16mc304 devices power their core digital logic at a nominal 2.5v. this can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system design, all devices in the dspic33fj32mc202/204 and dspic33fj16mc304 family incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator provides power to the core from the other v dd pins. when the regulator is enabled, a low-esr (less than 5 ohms) capacitor (such as tantalum or ceramic) must be connected to the v cap pin ( figure 21-1 ). this helps to maintain the stability of the regulator. the recommended value for the filter capac- itor is provided in table 24-13 located in section 24.1 ?dc characteristics? . on a por , it takes approximately 20 s for the on-chip voltage regulator to generate an output voltage. during this time, designated as t startup , code execution is disabled. t startup is applied every time the device resumes operation after any power-down. figure 21-1: connections for the on-chip voltage regulator (1,2,3) 21.3 bor: brown-out reset (bor) the brown-out reset (bor) module is based on an internal voltage reference circuit that monitors the reg- ulated supply voltage v cap . the main purpose of the bor module is to generate a device reset when a brown-out condition occurs. brown-out conditions are generally caused by glitches on the ac mains (for example, missing portions of the ac cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). a bor generates a reset pulse, which resets the device. the bor selects the clock source, based on the device configuration bit values (fnosc<2:0> and poscmd<1:0>). if an oscillator mode is selected, the bor activates the oscillator start-up timer (o st). the system clock is held until ost expires. if the pll is used, the clock is held until the lock bit (osccon<5>) is ? 1 ?. concurrently, the pwrt time -out (tpwrt) is applied before the internal reset is released. if tpwrt = 0 and a crystal oscillator is being used, then a nominal delay of tfscm = 100 is applied. the total delay in this case is tfscm. the bor status bit (rcon<1>) is set to indicate that a bor has occurred. the bor circuit continues to oper- ate while in sleep or idle modes and resets the device should v dd fall below the bor threshold voltage. note: it is important for low-esr capacitors to be placed as close as possible to the v cap pin. note 1: these are typical operating voltages. refer to table 24-13 located in section 24.1 ?dc characteristics? for the full operating ranges of v dd and v cap . 2: it is important for low-esr capacitors to be placed as close as possible to the v cap pin. 3: typical v cap pin voltage = 2.5v when v dd v ddmin . v dd v cap v ss dspic33f c efc 3.3v 10 f dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 216 ? 2007-2012 microchip technology inc. 21.4 watchdog timer (wdt) for dspic33fj32mc202/204 and dspic33fj16mc304 devices, the wdt is driven by the lprc oscillator. when the wdt is enabled, the clock source is also enabled. 21.4.1 prescaler/postscaler the nominal wdt clock source from lprc is 32 khz. this feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the wdtpre configuration bit. with a 32 khz input, the prescaler yields a nominal wdt time-out period (t wdt ) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the wdtpost<3:0> configuration bits (fwdt<3:0>), which allow the selec- tion of 16 settings, from 1:1 to 1:32,768. using the pres- caler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. the wdt, prescaler and postscaler are reset: ? on any device reset ? on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the nosc bits) or by hardware (i.e., fail-safe clock monitor) ? when a pwrsav instruction is executed (i.e., sleep or idle mode is entered) ? when the device exits sleep or idle mode to resume normal operation ?by a clrwdt instruction during normal execution 21.4.2 sleep and idle modes if the wdt is enabled, it will continue to run during sleep or idle modes. when the wdt time-out occurs, the device will wake the device and code execution will con- tinue from where the pwrsav instruction was executed. the corresponding sleep or idle bits (rcon<3,2>) will need to be cleared in softwa re after the device wakes up. 21.4.3 enabling wdt the wdt is enabled or disabled by the fwdten configuration bit in the fwdt configuration register. when the fwdten configuration bit is set, the wdt is always enabled. the wdt can be optionally controlled in software when the fwdten configuration bit has been programmed to ? 0 ?. the wdt is enabled in software by setting the swdten control bit ( rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user application to enable the wdt for critical code segments and disable the wdt during non-critical segments for maximum power savings. the wdt flag bit, wdto (rcon< 4>), is not automatically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. figure 21-2: wdt block diagram note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed. note: if the windis bit (fwdt<6>) is cleared, the clrwdt instruction should be executed by the application software only during the last 1/4 of the wdt period. this clrwdt window can be determined by using a timer. if a clrwdt instruction is executed before this window, a wdt reset occurs. all device resets transition to new clock source exit sleep or idle mode pwrsav instruction clrwdt instruction 0 1 wdtpre wdtpost<3:0> watchdog timer prescaler (divide by n1) postscaler (divide by n2) sleep/idle wdt wdt window select windis wdt clrwdt instruction swdten fwdten lprc clock rs rs wake-up reset ? 2007-2012 microchip technology inc. ds70283k-page 217 dspic33fj32mc202/204 and dspic33fj16mc304 21.5 jtag interface dspic33fj32mc202/204 and dspic33fj16mc304 devices implement a jtag interface, which supports boundary scan device testing, as well as in-circuit programming. detailed information on this interface will be provided in future revisions of the document. 21.6 in-circuit serial programming dspic33fj32mc202/204 and dspic33fj16mc304 family digital signal controllers can be serially programmed while in the end application circuit. this is done with two lines for clock and data and three other lines for power, ground and the programming sequence. serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. serial programming also allows the most recent firmware or a custom firmware to be programmed. refer to the ?dspic33f/pic24h flash programming specification? (ds70152) document for details about in-circuit serial programming (icsp). any of the three pairs of programming clock/data pins can be used: ? pgec1 and pged1 ? pgec2 and pged2 ? pgec3 and pged3 21.7 in-circuit debugger when mplab ? icd 2 is selected as a debugger, the in-circuit debugging functionality is enabled. this function allows simple debugging functions when used with mplab ide. debugging functionality is controlled through the pgecx (emulation/debug clock) and pgedx (emulation/debug data) pin functions. any of the three pairs of debugging clock/data pins can be used: ? pgec1 and pged1 ? pgec2 and pged2 ? pgec3 and pged3 to use the in-circuit debug ger function of the device, the design must implement icsp connections to mclr , v dd , v ss , and the pgecx/pgedx pin pair. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 218 ? 2007-2012 microchip technology inc. 21.8 code protection and codeguard? security the dspic33fj32mc202/204 and dspic33fj16mc304 devices offer the intermediate implementation of codeguard? security. codeguard security enables multiple parties to securely share resources (memory, interrupt s and peripherals) on a single chip. this feature helps protect individual intellectual pr operty in collabora tive system designs. when coupled with software encryption libraries, code- guard? security can be used to securely update flash even when multiple ips reside on the single chip. the code protection featur es are controlled by the configuration registers: fbs and fgs. secure segment and ram protection is not implemented in dspic 33fj32mc202/204 and dspic33fj16mc304 devices. table 21-3: code flash security segment sizes for 32 kbyte devices table 21-4: code flash security segment sizes for 16 kbyte devices note: refer to section 23. ?codeguard? security? (ds70199) in the ?dspic33f/pic24h family reference manual? for further information on usage, configuration and operation of codeguard security. config bits bss<2:0>=x11 0k bss<2:0>=x10 256 bss<2:0>=x01 768 bss<2:0>=x00 1792 0x0057fe 0x0001fe 0x000200 0x000000 vs = 256 iw 0x0007fe 0x000800 0x001ffe 0x002000 gs = 11008 iw 0x003ffe 0x004000 0x0057fe 0x0001fe 0x000200 0x000000 vs = 256 iw 0x0007fe 0x000800 0x001ffe 0x002000 0x003ffe 0x004000 gs = 10240 iw bs = 768 iw 0x0057fe 0x0001fe 0x000200 0x000000 vs = 256 iw 0x0007fe 0x000800 0x001ffe 0x002000 0x003ffe 0x004000 gs = 7168 iw bs = 3840 iw 0x0057fe 0x0001fe 0x000200 0x000000 vs = 256 iw 0x0007fe 0x000800 0x001ffe 0x002000 gs = 3072 iw 0x003ffe 0x004000 bs = 7936 iw config bits bss<2:0>=x11 0k bss<2:0>=x10 256 bss<2:0>=x01 768 bss<2:0>=x00 1792 0x002bfe 0x0001fe 0x000200 0x000000 vs = 256 iw 0x0007fe 0x000800 0x001ffe 0x002000 gs = 5376 iw 0x002bfe 0x0001fe 0x000200 0x000000 vs = 256 iw 0x0007fe 0x000800 0x001ffe 0x002000 gs = 4608 iw bs = 768 iw 0x002bfe 0x0001fe 0x000200 0x000000 vs = 256 iw 0x0007fe 0x000800 0x001ffe 0x002000 gs = 1536 iw bs = 3840 iw 0x002bfe 0x0001fe 0x000200 0x000000 vs = 256 iw 0x0007fe 0x000800 0x001ffe 0x002000 bs = 5376 iw ? 2007-2012 microchip technology inc. ds70283k-page 219 dspic33fj32mc202/204 and dspic33fj16mc304 22.0 instruction set summary the dspic33f instruction set is identical to that of the dspic30f. most instructions are a single program memory word (24 bits). only three instructions require two program memory locations. each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more oper ands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into five basic categories: ? word or byte-oriented operations ? bit-oriented operations ? literal operations ? dsp operations ? control operations table 22-1 shows the general symbols used in describing the instructions. the dspic33f instruct ion set summary in ta b l e 2 2 - 2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriente d w register instructions (including barrel shift instructions) have three operands: ? the first source operand, which is typically a register ?wb? without any address modifier ? the second source operand, which is typically a register ?ws? with or without an address modifier ? the destination of the result, which is typically a register ?wd? with or wit hout an address modifier however, word or byte-oriented file register instructions have two operands: ? the file register specified by the value ?f? ? the destination, which c ould be either the file register ?f? or the w0 regi ster, which is denoted as ?wreg? most bit-oriented instructions (including simple rotate/shift instructions) have two operands: ? the w register (with or without an address modifier) or file register (specified by the value of ?ws? or ?f?) ? the bit in the w register or file register (specified by a literal value or indirectly by the contents of register ?wb?) the literal instructions that involve data movement can use some of the following operands: ? a literal value to be loaded into a w register or file register (specified by ?k?) ? the w register or file register where the literal value is to be loaded (specified by ?wb? or ?f?) however, literal instructions that involve arithmetic or logical operations use some of the following operands: ? the first source operand, which is a register ?wb? without any address modifier ? the second source operand, which is a literal value ? the destination of the result (only if not the same as the first source operand), which is typically a register ?wd? with or without an address modifier the mac class of dsp instructions can use some of the following operands: ? the accumulator (a or b) to be used (required operand) ? the w registers to be used as the two operands ? the x and y address space prefetch operations ? the x and y address space prefetch destinations ? the accumulator write-back destination the other dsp instructions do not involve any multiplication and can include: ? the accumulator to be used (required) ? the source or destination operand (designated as wso or wdo, respectively) with or without an address modifier ? the amount of shift specif ied by a w register ?wn? or a literal value the control instructions can use some of the following operands: ? a program memory address ? the mode of the table read and table write instructions note: this data sheet summ arizes the features of the dspic33fj32mc202/204 and dspic33fj16mc304 devices. it is not intended to be a comprehensive refer- ence source. to comp lement the informa- tion in this data sheet, refer to the ?dspic33f/pic24h family reference manual? . please see the microchip web site ( www.microchip.com ) for the latest dspic33f/pic24h family reference manual sections. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 220 ? 2007-2012 microchip technology inc. most instructions are a single word. certain double-word instructions are designed to provide all the required information in these 48 bits. in the second word, the 8 msbs are ? 0 ?s. if this second word is exe- cuted as an instruction (by it self), it will execute as a nop . the double-word instructions execute in two instruction cycles. most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . notable exceptions are the bra (unconditional/computed branch), indirect call/goto , all table reads and writes and return/retfie instructions, which are single-word instructions but take two or three cycles. certain in structions that involve skip- ping over the subsequent inst ruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. note: for more details on the instruction set, refer to the ?16-bit mcu and dsc programmer?s reference manual? (ds70157). table 22-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation ? 2007-2012 microchip technology inc. ds70283k-page 221 dspic33fj32mc202/204 and dspic33fj16mc304 wm*wm multiplicand and multiplier working register pair for square instructions {w4 * w4,w5 * w5,w6 * w6,w7 * w7} wm*wn multiplicand and multiplier working register pair for dsp instructions {w4 * w5,w4 * w6,w4 * w7,w5 * w6,w5 * w7,w6 * w7} wn one of 16 working registers {w0..w15} wnd one of 16 destination working registers {w0...w15} wns one of 16 source working registers {w0...w15} wreg w0 (working register used in file register instructions) ws source w register { ws, [ws], [ws++], [ws --], [++ws], [--ws] } wso source w register { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } wx x data space prefetch address register for dsp instructions {[w8] + = 6, [w8] + = 4, [w8] + = 2, [w8], [w8] - = 6, [w8] - = 4, [w8] - = 2, [w9] + = 6, [w9] + = 4, [w9] + = 2, [w9], [w9] - = 6, [w9] - = 4, [w9] - = 2, [w9 + w12], none} wxd x data space prefetch destinati on register for dsp instructions {w4...w7} wy y data space prefetch address register for dsp instructions {[w10] + = 6, [w10] + = 4, [w10] + = 2, [w10], [w10] - = 6, [w10] - = 4, [w10] - = 2, [w11] + = 6, [w11] + = 4, [w11] + = 2, [w11], [w11] - = 6, [w11] - = 4, [w11] - = 2, [w11 + w12], none} wyd y data space prefetch destination register for dsp instructions {w4...w7} table 22-1: symbols used in opcode descriptions (continued) field description dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 222 ? 2007-2012 microchip technology inc. table 22-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected 1 add add acc add accumulators 1 1 oa,ob,sa,sb add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z add wso,#slit4,acc 16-bit signed add to accumulator 1 1 oa,ob,sa,sb 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3 and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n,z 5 bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6 bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra oa,expr branch if accumulator a overflow 1 1 (2) none bra ob,expr branch if accumulator b overflow 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra sa,expr branch if accumulator a saturated 1 1 (2) none bra sb,expr branch if accumulator b saturated 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none 7 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none 8 bsw bsw.c ws,wb write c bit to ws ? 2007-2012 microchip technology inc. ds70283k-page 223 dspic33fj32mc202/204 and dspic33fj16mc304 9 btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none 10 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 11 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none 12 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 224 ? 2007-2012 microchip technology inc. 29 div div.s wm,wn signed 16/16-bit integer divide 1 18 n,z,c,ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n,z,c,ov div.u wm,wn unsigned 16/16-bit integer divide 1 18 n,z,c,ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n,z,c,ov 30 divf divf wm,wn signed 16/16-bit fractional divide 1 18 n,z,c,ov 31 do do #lit14,expr do code to pc + expr, lit14 + 1 times 2 2 none do wn,expr do code to pc + expr, (wn) + 1 times 2 2 none 32 ed ed wm*wm,acc,wx,wy,wxd euclidean distance (no accumulate) 1 1 oa,ob,oab, sa,sb,sab 33 edac edac wm*wm,acc,wx,wy,wxd euclidean distance 1 1 oa,ob,oab, sa,sb,sab 34 exch exch wns,wnd swap wns with wnd 1 1 none 35 fbcl fbcl ws,wnd find bit change from left (msb) side 1 1 c 36 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 37 ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c 38 goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none 39 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 40 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 41 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 42 lac lac wso,#slit4,acc load accumulator 1 1 oa,ob,oab, sa,sb,sab 43 lnk lnk #lit14 link frame pointer 1 1 none 44 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n,z 45 mac mac wm*wn,acc,wx,wxd,wy,wyd , awb multiply and accumulate 1 1 oa,ob,oab, sa,sb,sab mac wm*wm,acc,wx,wxd,wy,wyd square and accumulate 1 1 oa,ob,oab, sa,sb,sab 46 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 n,z mov f,wreg move f to wreg 1 1 none mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 none mov.d wns,wd move double from w(ns):w(ns + 1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd + 1):w(nd) 1 2 none 47 movsac movsac acc,wx,wxd,wy,wyd,awb prefetch and store accumulator 1 1 none table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected ? 2007-2012 microchip technology inc. ds70283k-page 225 dspic33fj32mc202/204 and dspic33fj16mc304 48 mpy mpy wm*wn,acc,wx,wxd,wy,wyd multiply wm by wn to accumulator 1 1 oa,ob,oab, sa,sb,sab mpy wm*wm,acc,wx,wxd,wy,wyd square wm to accumulator 1 1 oa,ob,oab, sa,sb,sab 49 mpy.n mpy.n wm*wn,acc,wx,wxd,wy,wyd -(multiply wm by wn) to accumulator 1 1 none 50 msc msc wm*wm,acc,wx,wxd,wy,wyd , awb multiply and subtract from accumulator 1 1 oa,ob,oab, sa,sb,sab 51 mul mul.ss wb,ws,wnd {wnd + 1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd + 1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(ws) 1 1 none mul.su wb,#lit5,wnd {wnd + 1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(lit5) 1 1 none mul f w3:w2 = f * wreg 1 1 none 52 neg neg acc negate accumulator 1 1 oa,ob,oab, sa,sb,sab neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 53 nop nop no operation 1 1 none nopr no operation 1 1 none 54 pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd + 1) 1 2 none pop.s pop shadow registers 1 1 all 55 push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns + 1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none 56 pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto,sleep 57 rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none 58 repeat repeat #lit14 repeat next instruction lit14 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none 59 reset reset software device reset 1 1 none 60 retfie retfie return from interrupt 1 3 (2) none 61 retlw retlw #lit10,wn return with literal in wn 1 3 (2) none 62 return return return from subroutine 1 3 (2) none 63 rlc rlc f f = rotate left through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 64 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 65 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 226 ? 2007-2012 microchip technology inc. 66 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z 67 sac sac acc,#slit4,wdo store accumulator 1 1 none sac.r acc,#slit4,wdo store rounded accumulator 1 1 none 68 se se ws,wnd wnd = sign-extended ws 1 1 c,n,z 69 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none 70 sftac sftac acc,wn arithmetic shift accumulator by (wn) 1 1 oa,ob,oab, sa,sb,sab sftac acc,#slit6 arithmetic shift accumulator by slit6 1 1 oa,ob,oab, sa,sb,sab 71 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 72 sub sub acc subtract accumulators 1 1 oa,ob,oab, sa,sb,sab sub f f = f - wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f - wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn - lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb - ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb - lit5 1 1 c,dc,n,ov,z 73 subb subb f f = f - wreg - (c ) 1 1 c,dc,n,ov,z subb f,wreg wreg = f - wreg - (c ) 1 1 c,dc,n,ov,z subb #lit10,wn wn = wn - lit10 - (c ) 1 1 c,dc,n,ov,z subb wb,ws,wd wd = wb - ws - (c ) 1 1 c,dc,n,ov,z subb wb,#lit5,wd wd = wb - lit5 - (c ) 1 1 c,dc,n,ov,z 74 subr subr f f = wreg - f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg - f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws - wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 - wb 1 1 c,dc,n,ov,z 75 subbr subbr f f = wreg - f - (c ) 1 1 c,dc,n,ov,z subbr f,wreg wreg = wreg - f - (c ) 1 1 c,dc,n,ov,z subbr wb,ws,wd wd = ws - wb - (c ) 1 1 c,dc,n,ov,z subbr wb,#lit5,wd wd = lit5 - wb - (c ) 1 1 c,dc,n,ov,z 76 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 77 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none 78 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none 79 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 80 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 81 ulnk ulnk unlink frame pointer 1 1 none 82 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 83 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 22-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected ? 2007-2012 microchip technology inc. ds70283k-page 227 dspic33fj32mc202/204 and dspic33fj16mc304 23.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c ? for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/link er/librarian for various device families ? simulators - mplab sim software simulator ? emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstratio n/development boards, evaluation kits, and starter kits 23.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based app lication that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select thir d party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 228 ? 2007-2012 microchip technology inc. 23.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 23.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c comp ilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 23.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 23.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/libra ry features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 23.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable objec t files that can then be archived or linked with other relocatable object files and archives to create an execut able file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility ? 2007-2012 microchip technology inc. ds70283k-page 229 dspic33fj32mc202/204 and dspic33fj16mc304 23.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus c ontroller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 23.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated devel opment environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 23.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 23.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mp lab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connec ted to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 230 ? 2007-2012 microchip technology inc. 23.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environmen t (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the applicatio n. when halted at a break- point, the file registers ca n be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 23.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket asse mbly to support various package types. the icsp? ca ble assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc co nnection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorpor ates an mmc card for file storage and data applications. 23.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstr ation, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, sw itches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. ? 2007-2012 microchip technology inc. ds70283k-page 231 dspic33fj32mc202/204 and dspic33fj16mc304 24.0 electrical characteristics this section provides an overview of dspic33fj32mc 202/204 and dspic33fj16mc304 electrical characteristics. additional information will be provided in future re visions of this document as it becomes available. absolute maximum ratings for the dspic33fj32mc202/204 and dspic33fj16mc304 family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these or any other conditions above the parameters indica ted in the operation listings of this specification is not implied. absolute maximum ratings (1) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +160c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant with respect to v ss (4) .................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to vss when v dd 3.0v (4) .................................................... -0.3v to +5.6v voltage on any 5v tolerant pin with respect to v ss when v dd < 3.0v (4) ..................................................... -0.3v to 3.6v maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin (2) ...........................................................................................................................250 ma maximum current sourced/sunk by any 2x i/o pin (3) ................................................................................................8 ma maximum current sourced/sunk by any 4x i/o pin (3) ..............................................................................................15 ma maximum current sourced/sunk by any 8x i/o pin (3) ..............................................................................................25 ma maximum current sunk by all ports ......................... ..................................................................... .........................200 ma maximum current sourced by all ports (2) ...............................................................................................................200 ma note 1: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only, and functional o peration of the device at th ose or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 24-2 ). 3: exceptions are clkout, which is abl e to sink/source 25 ma, and the v ref +, v ref -, sclx, sdax, pgecx and pgedx pins, which are able to sink/source 12 ma. 4: refer to the ? pin diagrams ? section for 5v tolerant pins. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 232 ? 2007-2012 microchip technology inc. 24.1 dc characteristics table 24-1: operating mips vs. voltage characteristic v dd range (in volts) temp range (in c) max mips dspic33fj32mc202/204 and dspic33fj16mc304 ? v bor -3.6v (1) -40c to +85c 40 ? v bor -3.6v (1) -40c to +125c 40 note 1: device is functional at v bormin < v dd < v ddmin . analog modules such as the adc will have degraded performance. device functionality is tested but not characterized. refer to parameter bo10 in table 24-11 for the minimum and maximum bor values. table 24-2: thermal operating conditions rating symbol min typ max unit industrial temperature devices operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c extended temperature devices operating junction temperature range t j -40 ? +140 c operating ambient temperature range t a -40 ? +125 c power dissipation: internal chip power dissipation: p int = v dd x (i dd - i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ({v dd - v oh } x i oh ) + (v ol x i ol ) maximum allowed power dissipation p dmax (t j - t a )/ ja w table 24-3: thermal packaging characteristics characteristic symbol typ max unit notes package thermal resi stance, 44-pin qfn ja 32 ? c/w 1 package thermal resi stance, 44-pin tfqp ja 45 ? c/w 1 package thermal resi stance, 28-pin spdip ja 45 ? c/w 1 package thermal resistance, 28-pin soic ja 50 ? c/w 1 package thermal resi stance, 28-pin ssop ja 71 ? c/w 1 package thermal resist ance, 28-pin qfn-s ja 35 ? c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ja ) numbers are achieved by package simulations. ? 2007-2012 microchip technology inc. ds70283k-page 233 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions operating voltage dc10 supply voltage v dd ? 3.0 ? 3.6 v industrial and extended dc12 v dr ram data retention voltage (2) 1.8 ? ? v ? dc16 v por v dd start voltage to ensure internal power-on reset signal ??v ss v? dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.03 ? ? v/ms 0-3.0v in 0.1s note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: this is the limit to which v dd may be lowered without losing ram data. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 234 ? 2007-2012 microchip technology inc. table 24-5: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. (3) typical (2) max units conditions operating current (i dd ) (1) dc20d 20 30 ma -40c 3.3v 10 mips (3) dc20a 19 22 ma +25c dc20b 19 25 ma +85c dc20c 19 30 ma +125c dc21d 28 40 ma -40c 3.3v 16 mips (3) dc21a 27 30 ma +25c dc21b 27 32 ma +85c dc21c 27 36 ma +125c dc22d 33 50 ma -40c 3.3v 20 mips (3) dc22a 33 40 ma +25c dc22b 33 40 ma +85c dc22c 33 50 ma +125c dc23d 44 60 ma -40c 3.3v 30 mips (3) dc23a 43 50 ma +25c dc23b 42 55 ma +85c dc23c 41 65 ma +125c dc24d 55 75 ma -40c 3.3v 40 mips dc24a 54 65 ma +25c dc24b 52 70 ma +85c dc24c 51 80 ma +125c note 1: i dd is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code exec ution pattern and temperatur e, also have an impact on the current consumption. t he test conditions for all i dd measurements are as follows: ? oscillator is configured in ec mode with pll, os c1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) ? clko is configured as an i/o input pin in the configuration word ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? cpu, sram, program memory and data memory are operational ? no peripheral modules are operating; however, ever y peripheral is being clocked (defined pmdx bits are set to zero and unimplemented pmdx bits are set to one) ? cpu executing while(1) statement ? jtag is disabled 2: these parameters are characterized but not tested in manufacturing. 3: data in ?typ? column is at 3.3v, +25oc unless otherwise stated. ? 2007-2012 microchip technology inc. ds70283k-page 235 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. (3) typical (2) max units conditions idle current (i idle ): core off clock on base current (1) dc40d 7 20 ma -40c 3.3v 10 mips dc40a 6 7 ma +25c dc40b 6 10 ma +85c dc40c 6 20 ma +125c dc41d 10 20 ma -40c 3.3v 16 mips dc41a 8 ma +25c 9 dc41b 8 10 ma +85c dc41c 8 20 ma +125c dc42d 11 20 ma -40c 3.3v 20 mips dc42a 10 10 ma +25c dc42b 10 12 ma +85c dc42c 10 20 ma +125c dc43d 14 25 ma -40c 3.3v 30 mips dc43a 13 14 ma +25c dc43b 13 15 ma +85c dc43c 13 25 ma +125c dc44d 14 25 ma -40c 3.3v 40 mips dc44a 17 20 ma +25c dc44b 17 20 ma +85c dc44c 18 30 ma +125c note 1: base i idle current is measured as follows: ? cpu core is off, oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/ undershoot < 250 mv required) ? clko is configured as an i/o input pin in the configuration word ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? no peripheral modules are operating; however, ever y peripheral is being clocked (defined pmdx bits are set to zero and unimplemented pmdx bits are set to one) ? jtag is disabled 2: these parameters are characterized but not tested in manufacturing. 3: data in ?typ? column is at 3.3v, +25oc unless otherwise stated. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 236 ? 2007-2012 microchip technology inc. table 24-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. (3) typical (2) max units conditions power-down current (i pd ) (1) dc60d 55 500 a -40c 3.3v base power-down current (3,4) dc60a 63 300 a +25c dc60b 85 350 a +85c dc60c 146 600 a +125c dc61d 8 15 a -40c 3.3v watchdog timer current: i wdt (3,5) dc61a 2 3 a +25c dc61b 2 2 a +85c dc61c 3 5 a +125c note 1: i pd (sleep) current is measured as follows: ? cpu core is off, oscillator is configured in ec m ode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/unders hoot < 250 mv required) ? clko is configured as an i/o input pin in the configuration word ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled, all peripheral modules are disabled (pmdx bits are all ones) ? vregs bit (rcon<8>) = 0 (i.e., core regulator is set to stand-by while the device is in sleep mode) ? rtcc is disabled. ? jtag is disabled 2: data in the ?typ? column is at 3.3v, +25oc unless otherwise stated. 3: the watchdog timer current is the additional current consumed when the wdt module is enabled. this current should be added to the base i pd current. 4: these currents are measured on the device c ontaining the most memory in this family. 5: these parameters are characterized, but are not tested in manufacturing. ? 2007-2012 microchip technology inc. ds70283k-page 237 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-8: dc characteristics: doze current (i doze ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. (3) typical (2) max doze ratio units conditions doze current (i doze ) (1) dc73a 41 51 1:2 ma -40c 3.3v 40 mips dc73f 20 28 1:64 ma dc73g 19 24 1:128 ma dc70a 40 46 1:2 ma +25c 3.3v 40 mips dc70f 18 20 1:64 ma dc70g 18 20 1:128 ma dc71a 40 46 1:2 ma +85c 3.3v 40 mips dc71f 18 25 1:64 ma dc71g 18 20 1:128 ma dc72a 39 55 1:2 ma +125c 3.3v 40 mips dc72f 18 30 1:64 ma dc72g 18 25 1:128 ma note 1: i doze is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillato r type, internal code execution pattern and temperature, also have an impact on the current consumption. t he test conditions for all i doze measurements are as follows: ? oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail with overshoot/undershoot < 250 mv ? clko is configured as an i/o input pin in the configuration word ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd , wdt and fscm are disabled ? cpu, sram, program memory and data memory are operational ? no peripheral modules are operating; however, ever y peripheral is being clocked (defined pmdx bits are set to zero and unimplemented pmdx bits are set to one) ? cpu executing while(1) statement ? jtag is disabled 2: data in the ?typ? column is at 3.3v, +25oc unless otherwise stated. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 238 ? 2007-2012 microchip technology inc. table 24-9: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions v il input low voltage di10 i/o pins v ss ?0.2v dd v di15 mclr v ss ?0.2v dd v di16 i/o pins with osc1 or sosci v ss ?0.2v dd v di18 sdax, sclx v ss ? 0.3 v dd v smbus disabled di19 sdax, sclx v ss ? 0.8 v v smbus enabled v ih input high voltage di20 i/o pins not 5v tolerant (4) i/o pins 5v tolerant (4) 0.7 v dd 0.7 v dd ? ? v dd 5.5 v v di28 sdax, sclx 0.7 v dd ? 5.5 v smbus disabled di29 sdax, sclx 2.1 ? 5.5 v smbus enabled i cnpu cnx pull-up current di30 50 250 400 av dd = 3.3v, v pin = v ss note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher le akage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see ? pin diagrams ? for a list of digital-only and analog pins. 5: v il source < (v ss ? 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any ?positiv e? input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical ?absolute instantaneous? sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested. ? 2007-2012 microchip technology inc. ds70283k-page 239 dspic33fj32mc202/204 and dspic33fj16mc304 i il input leakage current (2,3) di50 i/o pins 5v tolerant (4) ??2 av ss v pin v dd , pin at high-impedance di51 i/o pins not 5v tolerant (4) ??1 av ss v pin v dd , pin at high-impedance, -40c t a +85c di51a i/o pins not 5v tolerant (4) ??2 a shared with external refer- ence pins, -40c t a +85c di51b i/o pins not 5v tolerant (4) ??3.5 av ss v pin v dd , pin at high-impedance, -40c t a +125c di51c i/o pins not 5v tolerant (4) ??8 a analog pins shared with external reference pins, -40c t a +125c di55 mclr ??2 av ss v pin v dd di56 osc1 ? ? 2 av ss v pin v dd , xt and hs modes table 24-9: dc characteristics: i/o pi n input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the app lied voltage level. the specified levels represent normal operating co nditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see ? pin diagrams ? for a list of digital-only and analog pins. 5: v il source < (v ss ? 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any ?positiv e? input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical ?absolute instantaneous? sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 240 ? 2007-2012 microchip technology inc. i icl input low injection current di60a 0 ? -5 (5,8) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , sosci, sosco, and rb14 i ich input high injection current di60b 0 ? +5 (6,7,8) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , sosci, sosco, rb14, and digital 5v-tolerant designated pins i ict total input injection current di60c (sum of all i/o and control pins) -20 (9) ?+20 (9) ma absolute instantaneous sum of all input injection currents from all i/o pins (| i icl + | i ich |) i ict table 24-9: dc characteristics: i/o pin input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher le akage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see ? pin diagrams ? for a list of digital-only and analog pins. 5: v il source < (v ss ? 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any ?positiv e? input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical ?absolute instantaneous? sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested. ? 2007-2012 microchip technology inc. ds70283k-page 241 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-10: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic mi n. typ. max. units conditions do10 v ol output low voltage i/o pins: 2x sink driver pins - all pins not defined by 4x or 8x driver pins ??0.4v i ol 3 ma, v dd = 3.3v output low voltage i/o pins: 4x sink driver pins - ra0, ra1, rb5, rb6, rb8, rb9, rb14 ??0.4v i ol 6 ma, v dd = 3.3v output low voltage i/o pins: 8x sink driver pins - osco, clko, ra3 ??0.4v i ol 10 ma, v dd = 3.3v do20 v oh output high voltage i/o pins: 2x source driver pins - all pins not defined by 4x or 8x driver pins 2.4 ? ? v i ol -3 ma, v dd = 3.3v output high voltage i/o pins: 4x source driver pins - ra0, ra1, rb5, rb6, rb8, rb9, rb14 2.4 ? ? v i ol -6 ma, v dd = 3.3v output high voltage i/o pins: 8x source driver pins - osco, clko, ra3 2.4 ? ? v i ol -10 ma, v dd = 3.3v do20a v oh 1 output high voltage i/o pins: 2x source driver pins - all pins not defined by 4x or 8x driver pins 1.5 ? ? v i oh -6 ma, v dd = 3.3v see note 1 2.0 ? ? i oh -5 ma, v dd = 3.3v see note 1 3.0 ? ? i oh -2 ma, v dd = 3.3v see note 1 output high voltage 4x source driver pins - ra0, ra1, rb5, rb6, rb8, rb9, rb14 1.5 ? ? v i oh -12 ma, v dd = 3.3v see note 1 2.0 ? ? i oh -11 ma, v dd = 3.3v see note 1 3.0 ? ? i oh -3 ma, v dd = 3.3v see note 1 output high voltage 8x source driver pins - osco, clko, ra3 1.5 ? ? v i oh -16 ma, v dd = 3.3v see note 1 2.0 ? ? i oh -12 ma, v dd = 3.3v see note 1 3.0 ? ? i oh -4 ma, v dd = 3.3v see note 1 note 1: parameters are characterized, but not tested. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 242 ? 2007-2012 microchip technology inc. table 24-11: electrical characteristics: bor dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions bo10 v bor bor event on v dd transition 2.40 ? 2.55 v see note 2 note 1: parameters are for design guidance only and are not tested in manufacturing. 2: device is functional at v bormin < v dd < v ddmin . analog modules such as the adc will have degraded performance. device functionality is tested but not characterized. table 24-12: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (3) min typ (1) max units conditions program flash memory d130 e p cell endurance 10,000 ? ? e/w -40 c to +125 c d131 v pr v dd for read v min ?3.6vv min = minimum operating voltage d132b v pew v dd for self-timed write v min ?3.6vv min = minimum operating voltage d134 t retd characteristic retention 20 ? ? year p rovided no other specifications are violated, -40 c to +125 c d135 i ddp supply current during programming ?10 ?ma d136a t rw row write time 1.32 ? 1.74 ms t rw = 11064 frc cycles, t a = +85c, see note 2 d136b t rw row write time 1.28 ? 1.79 ms t rw = 11064 frc cycles, t a = +150c, see note 2 d137a t pe page erase time 20.1 ? 26.5 ms t pe = 168517 frc cycles, t a = +85c, see note 2 d137b t pe page erase time 19.5 ? 27.3 ms t pe = 168517 frc cycles, t a = +150c, see note 2 d138a t ww word write cycle time 42.3 ? 55.9 st ww = 355 frc cycles, t a = +85c, see note 2 d138b t ww word write cycle time 41.1 ? 57.6 st ww = 355 frc cycles, t a = +150c, see note 2 note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: other conditions: frc = 7.37 mhz, tun<5:0> = b'011111 (for min), tun<5:0> = b'100000 (for max). this parameter depends on the frc accuracy (see table 24-18 ) and the value of the frc oscillator tun- ing register (see register 8-4 ). for complete details on calculatin g the minimum and maximum time see section 5.3 ?programming operations? . 3: these parameters are assured by design, but are not characterized or tested in manufacturing. ? 2007-2012 microchip technology inc. ds70283k-page 243 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-13: internal voltage regulator specifications standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristics min typ max units comments ?c efc external filter capacitor value (1) 4.7 10 ? f capacitor must be low series resistance (< 5 ohms) note 1: typical v cap voltage = 2.5v when v dd v ddmin . dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 244 ? 2007-2012 microchip technology inc. 24.2 ac characteristics and timing parameters this section defines dspic33fj32mc202/204 and dspic33fj16mc304 ac characteristics and timing parameters. table 24-14: temperature and voltage specifications ? ac figure 24-1: load conditions for device timing specifications table 24-15: capacitive loading requirements on output pins ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in table 24-1 . param no. symbol characteristic min typ max units conditions do50 c osc 2 osc2/sosc2 pin ? ? 15 pf in xt and hs modes when external clock is used to drive osc1 do56 c io all i/o pins and osc2 ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 ? for all pins except osc2 load condition 2 ? for osc2 ? 2007-2012 microchip technology inc. ds70283k-page 245 dspic33fj32mc202/204 and dspic33fj16mc304 figure 24-2: external clock timing q1 q2 q3 q4 osc1 clko q1 q2 q3 q4 os20 os25 os30 os30 os40 os41 os31 os31 table 24-16: external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symb characteristic min typ (1) max units conditions os10 f in external clki frequency (4) (external clocks allowed only in ec and ecpll modes) dc ? 40 mhz ec oscillator crystal frequency (5) 3.5 10 ? ? ? 10 40 33 mhz mhz khz xt hs sosc os20 t osc t osc = 1/f osc (4) 12.5 ? dc ns ? os25 t cy instruction cycle time (2,4) 25 ? dc ns ? os30 tosl, to s h external clock in (osc1) (5) high or low time 0.375 x t osc ? 0.625 x t osc ns ec os31 tosr, to s f external clock in (osc1) (5) rise or fall time ??20nsec os40 tckr clko rise time (3,5) ?5.2?ns? os41 tckf clko fall time (3,5) ?5.2?ns? os42 g m external oscillator transconductance (6) 14 16 18 ma/v v dd = 3.3v t a = +25oc note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: instruction cycle period (t cy ) equals two times the input oscillator time-base period. all specified values are based on characterization data fo r that particular oscillator type under standard operating conditions with the device executing code. exc eeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/c lki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. 3: measurements are taken in ec mode. the cl ko signal is measured on the osc2 pin. 4: these parameters are characterized by simila rity, but are tested in manufacturing at f in = 40 mhz only. 5: these parameters are characterized by simila rity, but are not tested in manufacturing. 6: data for this parameter is preliminary. this parameter is characterized, but is not tested in manufacturing. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 246 ? 2007-2012 microchip technology inc. table 24-17: pll clock timing specifications (v dd = 3.0v to 3.6v) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range (2) 0.8 ? 8 mhz ecpll, xtpll modes os51 f sys on-chip vco system frequency (3) 100 ? 200 mhz ? os52 t lock pll start-up time (lock time) (3) 0.9 1.5 3.1 ms ? os53 d clk clko stability (jitter) (3) -3 0.5 3 % measured over 100 ms period note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: these parameters are characterized by similarity, bu t are tested in manufacturing at 7.7 mhz input only. 3: these parameters are characterized by similarity, but ar e not tested in manufacturi ng. this specification is based on clock cycle by clock cycle measurements. to calc ulate the effective jitter for individual time bases or communication clocks use this formula: peripheral clock jitter d clk f osc peripheral bit rate clock -------------------------------------------------------------- ?? ?? ----------------------------------------------------------------------- - = for example: fosc = 32 mhz, d clk = 3%, spi bit rate clock, (i.e., sck) is 2 mhz. spi sck jitter d clk 32 mhz 2 mhz -------------------- ?? ?? ------------------------------ 3% 16 --------- - 3% 4 ------- - 0.75% ==== table 24-18: ac characteristics: internal rc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c ta +85c for industrial -40c t a +125c for extended param no. characteristic min typ max units conditions internal frc accuracy @ frc frequency = 7.37 mhz (1) f20a frc -2 ? +2 % -40c t a +85c v dd = 3.0-3.6v f20b frc -5 ? +5 % -40c t a +125c v dd = 3.0-3.6v note 1: frequency calibrated at 25c and 3.3v. tun bits can be used to compensate for temperature drift. table 24-19: internal rc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min typ max units conditions lprc @ 32.768 khz (1,2) f21a lprc -15 6 +15 % -40c t a +85c v dd = 3.0-3.6v f21b lprc -40 ? +40 % -40c t a +125c v dd = 3.0-3.6v note 1: change of lprc frequency as v dd changes. 2: lprc impacts the watchdog timer time-out period (t wdt 1). see section 21.4 ?watchdog timer (wdt)? for more information. ? 2007-2012 microchip technology inc. ds70283k-page 247 dspic33fj32mc202/204 and dspic33fj16mc304 figure 24-3: i/o timing characteristics table 24-20: i/o timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (2) min typ (1) max units conditions do31 t io r port output rise time ? 10 25 ns ? do32 t io f port output fall time ? 10 25 ns ? di35 t inp intx pin high or low time (input) 25 ? ? ns ? di40 t rbp cnx high or low time (input) 2 ? ? t cy ? note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: these parameters are characterized, but are not tested in manufacturing. note: refer to figure 24-1 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 248 ? 2007-2012 microchip technology inc. figure 24-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing characteristics v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset sy11 sy10 sy20 sy13 i/o pins sy13 note: refer to figure 24-1 for load conditions. fscm delay sy35 sy30 sy12 ? 2007-2012 microchip technology inc. ds70283k-page 249 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-21: reset, watchdog timer, osci llator start-up timer, power-up timer timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (2) max units conditions sy10 t mc lmclr pulse width (low) (1) 2 ? ? s -40c to +85c sy11 t pwrt power-up timer period (1) ?2 4 8 16 32 64 128 ? ms -40c to +85c user programmable sy12 t por power-on reset delay (3) 31030 s -40c to +85c sy13 t ioz i/o high-impedance from mclr low or watchdog timer reset (1) 0.68 0.72 1.2 s? sy20 t wdt 1 watchdog timer time-out period (1) ? ? ? ms see section 21.4 ?watchdog timer (wdt)? and lprc parameter f21a ( table 24-21 ). sy30 t ost oscillator start-up time ? 1024 t osc ??t osc = osc1 period sy35 t fscm fail-safe clock monitor delay (1) ? 500 900 s -40c to +85c note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: these parameters are characterized by simila rity, but are not tested in manufacturing. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 250 ? 2007-2012 microchip technology inc. figure 24-5: timer1, 2 and 3 external clock timing characteristics note: refer to figure 24-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 24-22: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (2) min typ max units conditions ta10 t tx h txck high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter ta15 synchronous, with prescaler 10 ? ? ns asynchronous 10 ? ? ns ta11 t tx l txck low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns must also meet parameter ta15 synchronous, with prescaler 10 ? ? ns asynchronous 10 ? ? ns ta15 t tx p txck input period synchronous, no prescaler t cy + 40 ? ? ns ? synchronous, with prescaler greater of: 20 ns or (t cy + 40)/n ? ? ? n = prescale value (1, 8, 64, 256) asynchronous 20 ? ? ns ? os60 ft1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting bit tcs (t1con<1>)) dc ? 50 khz ? ta20 t ckextmrl delay from external txck clock edge to timer increment 0.5 t cy 1.5 t cy ?? note 1: timer1 is a type a. 2: these parameters are characterized by simila rity, but are not tested in manufacturing. ? 2007-2012 microchip technology inc. ds70283k-page 251 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-23: timer2 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions tb10 ttxh txck high time synchronous mode greater of: 20 or (t cy + 20)/n ??ns must also meet parameter tb15 n = prescale value (1, 8, 64, 256) tb11 ttxl txck low time synchronous mode greater of: 20 or (t cy + 20)/n ? ? ns must also meet parameter tb15 n = prescale value (1, 8, 64, 256) tb15 ttxp txck input period synchronous mode greater of: 40 or (2 t cy + 40)/n ? ? ns n = prescale value (1, 8, 64, 256) tb20 t ckextmrl delay from external txck clock edge to timer incre- ment 0.75 t cy + 40 ? 1.75 t cy + 40 ns ? note 1: these parameters are characterized, but are not tested in manufacturing. table 24-24: timer3 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions tc10 ttxh txck high time synchronous t cy + 20 ? ? ns must also meet parameter tc15 tc11 ttxl txck low time synchronous t cy + 20 ? ? ns must also meet parameter tc15 tc15 ttxp txck input period synchronous, with prescaler 2 t cy + 40 ? ? ns n = prescale value (1, 8, 64, 256) tc20 t ckextmrl delay from external txck clock edge to timer incre- ment 0.75 t cy + 40 ? 1.75 t cy + 40 ns ? note 1: these parameters are characterized, but are not tested in manufacturing. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 252 ? 2007-2012 microchip technology inc. figure 24-6: timerq (qei module) external clock timing characteristics tq11 tq15 tq10 tq20 qeb poscnt table 24-25: qei module external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions tq10 ttqh tqck high time synchronous, with prescaler t cy + 20 ? ? ns must also meet parameter tq15 tq11 ttql tqck low time synchronous, with prescaler t cy + 20 ? ? ns must also meet parameter tq15 tq15 ttqp tqcp input period synchronous, with prescaler 2 * t cy + 40 ? ? ns ? tq20 t ckextmrl delay from external txck clock edge to timer increment 0.5 t cy ? 1.5 t cy ?? note 1: these parameters are characterized but not tested in manufacturing. ? 2007-2012 microchip technology inc. ds70283k-page 253 dspic33fj32mc202/204 and dspic33fj16mc304 figure 24-7: input capture (capx) timing characteristics figure 24-8: output compare module (ocx) timing characteristics table 24-26: input capture timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min max units conditions ic10 tccl icx input low time no prescaler 0.5 t cy + 20 ? ns ? with prescaler 10 ? ns ic11 tcch icx input high time no prescaler 0.5 t cy + 20 ? ns ? with prescaler 10 ? ns ic15 tccp icx input period (t cy + 40)/n ? ns n = prescale value (1, 4, 16) note 1: these parameters are characterized but not tested in manufacturing. table 24-27: output compare module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions oc10 tccf ocx output fall time ? ? ? ns see parameter d032 oc11 tccr ocx output rise time ? ? ? ns see parameter d031 note 1: these parameters are characterized but not tested in manufacturing. icx ic10 ic11 ic15 note: refer to figure 24-1 for load conditions. ocx oc11 oc10 (output compare note: refer to figure 24-1 for load conditions. or pwm mode) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 254 ? 2007-2012 microchip technology inc. figure 24-9: oc/pwm module ti ming characteristics ocfa ocx oc20 oc15 active tri-state table 24-28: simple oc/pwm mode timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions oc15 t fd fault input to pwm i/o change ??t cy + 20 ns ? oc20 t flt fault input pulse-width t cy + 20 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. ? 2007-2012 microchip technology inc. ds70283k-page 255 dspic33fj32mc202/204 and dspic33fj16mc304 figure 24-10: motor control pwm module fault timing characteristics figure 24-11: motor control pwm mo dule timing characteristics flta pwmx mp30 mp20 pwmx mp11 mp10 note: refer to figure 24-1 for load conditions. table 24-29: motor control pw m module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions mp10 t fpwm pwm output fall time ? ? ? ns see parameter d032 mp11 t rpwm pwm output rise time ? ? ? ns see parameter d031 mp20 t fd fault input to pwm i/o change ??50ns ? mp30 t fh minimum pulse-width 50 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 256 ? 2007-2012 microchip technology inc. figure 24-12: qea/qeb input characteristics tq30 tq35 tq31 qea (input) tq30 tq35 tq31 qeb (input) tq36 qeb internal tq40 tq41 table 24-30: quadrature decoder timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) typ (2) max units conditions tq30 t qu l quadrature input low time 6 t cy ?ns ? tq31 t qu h quadrature input high time 6 t cy ?ns ? tq35 t qu in quadrature input period 12 t cy ?ns ? tq36 t qu p quadrature phase period 3 t cy ?ns ? tq40 t quf l filter time to recognize low, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 3) tq41 t quf h filter time to recognize high, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 3) note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherw ise stated. parameters are for design guidance only and are not tested. 3: n = index channel digital filter clock divide select bits. refer to section 15. ?quadrature encoder interface (qei)? (ds70208) in the ? dspic33f/pic24h family reference manual ?. please see the microchip web site for the latest dspic33f/pic24h family reference manual sections. ? 2007-2012 microchip technology inc. ds70283k-page 257 dspic33fj32mc202/204 and dspic33fj16mc304 figure 24-13: qei module index pulse timing characteristics qea (input) ungated index qeb (input) tq55 index internal position coun- ter reset tq50 tq51 table 24-31: qei index pulse timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min max units conditions tq50 tqil filter time to recognize low, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 2) tq51 tqih filter time to recognize high, with digital filter 3 * n * t cy ? ns n = 1, 2, 4, 16, 32, 64, 128 and 256 (note 2) tq55 tqidxr index pulse recognized to position counter reset (ungated index) 3 t cy ?ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: alignment of index pulses to qea and qeb is shown for position counter reset timing only. shown for forward direction only (qea leads qeb). same timing applies for reverse direction (qea lags qeb) but index pulse recognition occurs on falling edge. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 258 ? 2007-2012 microchip technology inc. table 24-32: spix maximum data/clock rate summary figure 24-14: spix master mode (h alf-duplex, transmit only cke = 0 ) timing characteristics ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended maximum data rate master transmit only (half-duplex) master transmit/receive (full-duplex) slave transmit/receive (full-duplex) cke ckp smp 15 mhz table 24-33 ?? 0 , 10 , 10 , 1 9 mhz ? table 24-34 ? 10 , 11 9 mhz ? table 24-35 ? 00 , 11 15 mhz ? ? table 24-36 100 11 mhz ? ? table 24-37 110 15 mhz ? ? table 24-38 010 11 mhz ? ? table 24-39 000 sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 24-1 for load conditions. ? 2007-2012 microchip technology inc. ds70283k-page 259 dspic33fj32mc202/204 and dspic33fj16mc304 figure 24-15: spix master mode (h alf-duplex, transmit only cke = 1 ) timing characteristics table 24-33: spix master mode (half-duplex, transmit only) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscp maximum sck frequency ? ? 15 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns ? sp36 tdiv2sch, tdiv2scl sdox data output setup to first sckx edge 30 ? ? ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. theref ore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 24-1 for load conditions. sp36 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 260 ? 2007-2012 microchip technology inc. figure 24-16: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing characteristics table 24-34: spix master mo de (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscp maximum sck frequency ? ? 9 mhz see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 24-1 for load conditions. sp36 sp41 msb in lsb in bit 14 - - - -1 sdix sp40 ? 2007-2012 microchip technology inc. ds70283k-page 261 dspic33fj32mc202/204 and dspic33fj16mc304 figure 24-17: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing characteristics table 24-35: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscp maximum sck frequency ? ? 9 mhz -40oc to +125oc and see note 3 sp20 tscf sckx output fall time ? ? ? ns see parameter do32 and note 4 sp21 tscr sckx output rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? 6 20 ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 24-1 for load conditions. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 262 ? 2007-2012 microchip technology inc. figure 24-18: spix slave mode (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 24-1 for load conditions. ? 2007-2012 microchip technology inc. ds70283k-page 263 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-36: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscp maximum sck input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ??50ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. ther efore, the sck clock gener ated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 264 ? 2007-2012 microchip technology inc. figure 24-19: spix slave mode (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 24-1 for load conditions. ? 2007-2012 microchip technology inc. ds70283k-page 265 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-37: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscp maximum sck input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge ??50ns ? note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. theref ore, the sck clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 266 ? 2007-2012 microchip technology inc. figure 24-20: spix slave mode (full-duplex cke = 0 , ckp = 1 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 24-1 for load conditions. sdi x ? 2007-2012 microchip technology inc. ds70283k-page 267 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-38: spix slave mo de (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscp maximum sck input frequency ? ? 15 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. ther efore, the sck clock gener ated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 268 ? 2007-2012 microchip technology inc. figure 24-21: spix slave mode (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 24-1 for load conditions. sdi x ? 2007-2012 microchip technology inc. ds70283k-page 269 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-39: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscp maximum sck input frequency ? ? 11 mhz see note 3 sp72 tscf sckx input fall time ? ? ? ns see parameter do32 and note 4 sp73 tscr sckx input rise time ? ? ? ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ? ? ? ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ? ? ? ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?620ns ? sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ? ? ns ? sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ? ? ns ? sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ? ? ns ? sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ? ? ns ? sp51 tssh2doz ssx to sdox output high-impedance (4) 10 ? 50 ns ? sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ? ? ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. theref ore, the sck clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 270 ? 2007-2012 microchip technology inc. figure 24-22: i2cx bus start/stop bits timing characteristics (master mode) figure 24-23: i2cx bus data timing characteristics (master mode) im31 im34 sclx sdax start condition stop condition im30 im33 note: refer to figure 24-1 for load conditions. im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 24-1 for load conditions. ? 2007-2012 microchip technology inc. ds70283k-page 271 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-40: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (3) min (1) max units conditions im10 t lo : scl clock low time 100 khz mode t cy /2 (brg + 1) ? s? 400 khz mode t cy /2 (brg + 1) ? s? 1 mhz mode (2) t cy /2 (brg + 1) ? s? im11 t hi : scl clock high time 100 khz mode t cy /2 (brg + 1) ? s? 400 khz mode t cy /2 (brg + 1) ? s? 1 mhz mode (2) t cy /2 (brg + 1) ? s? im20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 100 ns im21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) ? 300 ns im25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (2) 40 ? ns im26 t hd : dat data input hold time 100 khz mode 0 ? s? 400 khz mode 0 0.9 s 1 mhz mode (2) 0.2 ? s im30 t su : sta start condition setup time 100 khz mode t cy /2 (brg + 1) ? s only relevant for repeated start condition 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im31 t hd : sta start condition hold time 100 khz mode t cy /2 (brg + 1) ? s after this period the first clock pulse is generated 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im33 t su : sto stop condition setup time 100 khz mode t cy /2 (brg + 1) ? s? 400 khz mode t cy /2 (brg + 1) ? s 1 mhz mode (2) t cy /2 (brg + 1) ? s im34 t hd : sto stop condition 100 khz mode t cy /2 (brg + 1) ? ns ? hold time 400 khz mode t cy /2 (brg + 1) ? ns 1 mhz mode (2) t cy /2 (brg + 1) ? ns im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns ? 400 khz mode ? 1000 ns ? 1 mhz mode (2) ? 400 ns ? im45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (2) 0.5 ? s im50 c b bus capacitive loading ? 400 pf ? im51 t pgd pulse gobbler delay 65 390 ns see note 4 note 1: brg is the value of the i 2 c baud rate generator. refer to section 19. ?inter-integrated circuit (i 2 c?)? (ds70195) in the ? dspic33f/pic24h family reference manual?. please see the microchip web site for the latest dspic33f/pic24h family reference manual sections. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: these parameters are characterized by simila rity, but are not tested in manufacturing. 4: typical value for this parameter is 130 ns. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 272 ? 2007-2012 microchip technology inc. figure 24-24: i2cx bus start/stop bits timing characteristics (slave mode) figure 24-25: i2cx bus data timing characteristics (slave mode) is31 is34 sclx sdax start condition stop condition is30 is33 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out ? 2007-2012 microchip technology inc. ds70283k-page 273 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-41: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic (2) min max units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 ? s? is11 t hi : scl clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 ? s? is20 t f : scl sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns is21 t r : scl sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns is25 t su : dat data input setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode (1) 100 ? ns is26 t hd : dat data input hold time 100 khz mode 0 ? s? 400 khz mode 0 0.9 s 1 mhz mode (1) 00.3 s is30 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is31 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 1 mhz mode (1) 0.25 ? s is33 t su : sto stop condition setup time 100 khz mode 4.7 ? s? 400 khz mode 0.6 ? s 1 mhz mode (1) 0.6 ? s is34 t hd : st o stop condition hold time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode (1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns ? 400 khz mode 0 1000 ns 1 mhz mode (1) 0 350 ns is45 t bf : sda bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s 1 mhz mode (1) 0.5 ? s is50 c b bus capacitive loading ? 400 pf ? note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 2: these parameters are characterized by simila rity, but are not tested in manufacturing. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 274 ? 2007-2012 microchip technology inc. table 24-42: adc module specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symb ol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply (2) greater of v dd ? 0.3 or 3.0 ? lesser of v dd + 0.3 or 3.6 v ? ad02 av ss module v ss supply (2) v ss ? 0.3 ? v ss + 0.3 v ? reference inputs ad05 v refh reference voltage high av ss + 2.5 ? av dd vsee note 1 ad05a 3.0 ? 3.6 v v refh = av dd v refl = av ss = 0, see note 2 ad06 v refl reference voltage low av ss ?av dd ? 2.5 v see note 1 ad06a 0 ? 0 v v refh = av dd v refl = av ss = 0, see note 2 ad07 v ref absolute reference voltage (2) 2.5 ? 3.6 v v ref = v refh - v refl ad08 i ref current drain ? ? 250 ? 550 10 a a adc operating, see note 1 adc off, see note 1 ad08a i ad operating current ? ? 7.0 2.7 9.0 3.2 ma ma 10-bit adc mode, see note 2 12-bit adc mode, see note 2 analog input ad12 v inh input voltage range v inh (2) v inl ?v refh v this voltage reflects sample and hold channels 0, 1, 2, and 3 (ch0-ch3), positive input ad13 v inl input voltage range v inl (2) v refl ?av ss + 1v v this voltage reflects sample and hold channels 0, 1, 2, and 3 (ch0-ch3), negative input ad17 r in recommended impedance of analog voltage source (3) ? ? ? ? 200 200 10-bit adc 12-bit adc note 1: these parameters are not characterized or tested in manufacturing. 2: these parameters are characterized, but are not tested in manufacturing. 3: these parameters are assured by design, but ar e not characterized or tested in manufacturing. ? 2007-2012 microchip technology inc. ds70283k-page 275 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-43: adc module specifications (12-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions adc accuracy (12-bit mode) ? measurements with external v ref +/v ref - (3) ad20a nr resolution (4) 12 data bits bits ? ad21a inl integral nonlinearity -2 ? +2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad22a dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad23a g err gain error ? 3.4 10 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad24a e off offset error ? 0.9 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad25a ? monotonicity ? ? ? ? guaranteed (1) adc accuracy (12-bit mode) ? me asurements with internal v ref +/v ref - (3) ad20a nr resolution (4) 12 data bits bits ? ad21a inl integral nonlinearity -2 ? +2 lsb v inl = av ss = 0v, av dd = 3.6v ad22a dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = 0v, av dd = 3.6v ad23a g err gain error ? 10.5 20 lsb v inl = av ss = 0v, av dd = 3.6v ad24a e off offset error ? 3.8 10 lsb v inl = av ss = 0v, av dd = 3.6v ad25a ? monotonicity ? ? ? ? guaranteed (1) dynamic performance (12-bit mode) (2) ad30a thd total harmonic distortion ? ? -75 db ? ad31a sinad signal to noise and distortion 68.5 69.5 ? db ? ad32a sfdr spurious free dynamic range 80 ? ? db ? ad33a f nyq input signal bandwidth ? ? 250 khz ? ad34a enob effective number of bits 11.09 11.3 ? bits ? note 1: the a/d conversion result never de creases with an increase in the input voltage, and has no missing codes. 2: these parameters are characterized by simila rity, but are not tested in manufacturing. 3: these parameters are characterized, but are tested at 20 ksps only. 4: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 276 ? 2007-2012 microchip technology inc. table 24-44: adc module specifications (10-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions adc accuracy (10-bit mode) ? measurements with external v ref +/v ref - (3) ad20b nr resolution (4) 10 data bits bits ? ad21b inl integral nonlinearity -1.5 ? +1.5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad22b dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad23b g err gain error ? 3 6 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad24b e off offset error ? 2 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad25b ? monotonicity ? ? ? ? guaranteed (1) adc accuracy (10-bit mode) ? me asurements with internal v ref +/v ref - (3) ad20b nr resolution (4) 10 data bits bits ? ad21b inl integral nonlinearity -1 ? +1 lsb v inl = av ss = 0v, av dd = 3.6v ad22b dnl differential nonlinearity >-1 ? <1 lsb v inl = av ss = 0v, av dd = 3.6v ad23b g err gain error ? 7 15 lsb v inl = av ss = 0v, av dd = 3.6v ad24b e off offset error ? 3 7 lsb v inl = av ss = 0v, av dd = 3.6v ad25b ? monotonicity ? ? ? ? guaranteed (1) dynamic performance (10-bit mode) (2) ad30b thd total harmonic distortion ? ? -64 db ? ad31b sinad signal to noise and distortion 57 58.5 ? db ? ad32b sfdr spurious free dynamic range 72 ? ? db ? ad33b f nyq input signal bandwidth ? ? 550 khz ? ad34b enob effective number of bits 9.16 9.4 ? bits ? note 1: the a/d conversion result never de creases with an increase in the input voltage, and has no missing codes. 2: these parameters are characterized by simila rity, but are not tested in manufacturing. 3: these parameters are characterized, but are tested at 20 ksps only. 4: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. ? 2007-2012 microchip technology inc. ds70283k-page 277 dspic33fj32mc202/204 and dspic33fj16mc304 figure 24-26: adc conversion (12-bit mode) timing characteristics (asam = 0 , ssrc<2:0> = 000 ) table 24-45: adc conversion (12- bit mode) timing requirements ad55 t samp clear samp set samp ad61 adclk instruction samp ad60 done ad1if 1 2 3 4 5 6 8 7 1 ? software sets ad1con. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in 3 ? software clears ad1con. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 11. 9 ? one t ad for end of conversion. ad50 9 6 ? convert bit 10. 7 ? convert bit 1. 8 ? convert bit 0. execution in the ?dspic33f/pic24h family reference manual? . section 16. ?analog-to-digital converter (adc)? (ds70183) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions clock parameters ad50 t ad adc clock period (2) 117.6 ? ? ns ? ad51 t rc adc internal rc oscillator period (2) ? 250 ? ns ? conversion rate ad55 t conv conversion time (2) ? 14 t ad ?ns ? ad56 f cnv throughput rate (2) ??500ksps ? ad57 t samp sample time (2) 3.0 t ad ?? ? ? timing parameters ad60 t pcs conversion start from sample trigger (2) 2.0 t ad ? 3.0 t ad ? auto convert trigger not selected ad61 t pss sample start from setting sample (samp) bit (2) 2.0 t ad ? 3.0 t ad ?? ad62 t css conversion completion to sample start (asam = 1 ) (2) ? 0.5 t ad ?? ? ad63 t dpu time to stabilize analog stage from adc off to adc on (2) ??20 s? note 1: because the sample caps will eventually lose charge, clock rates below 10 khz may affect linearity performance, especially at elevated temperatures. 2: these parameters are characterized but not tested in manufacturing. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 278 ? 2007-2012 microchip technology inc. figure 24-27: adc conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 0 , ssrc<2:0> = 000 ) figure 24-28: adc conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 1 , ssrc<2:0> = 111 , samc<4:0> = 00001 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ad60 done ad1if 1 2 3 4 5 6 8 5 6 7 1 ? software sets ad1con. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in 3 ? software clears ad1con. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 9. 8 ? one t ad for end of conversion. ad50 7 ad55 8 6 ? convert bit 8. 7 ? convert bit 0. execution in the ?dspic33f/pic24h family reference manual? . section 16. ?analog-to-digital converter (adc)? (ds70183) 1 2 3 4 5 6 4 5 6 8 1 ? software sets ad1con. adon to start ad operation. 2 ? sampling starts after discharge period. t samp is described in 3 ? convert bit 9. 4 ? convert bit 8. 5 ? convert bit 0. 7 3 6 ? one t ad for end of conversion. 7 ? begin conversion of next channel. 8 ? sample for time specified by samc<4:0>. adclk instruction set adon execution samp t samp ad1if done ad55 ad55 t samp ad55 ad50 section 16. ?analog-to-digital converter (adc)? (ds70183) in the ?dspic33f/pic24h family reference manual? . ? 2007-2012 microchip technology inc. ds70283k-page 279 dspic33fj32mc202/204 and dspic33fj16mc304 table 24-46: adc conversion (10- bit mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ (1) max. units conditions clock parameters ad50 t ad adc clock period (1) 76 ? ? ns ? ad51 t rc adc internal rc oscillator period (1) ? 250 ? ns ? conversion rate ad55 t conv conversion time (1) ?12 t ad ?? ? ad56 f cnv throughput rate (1) ??1.1msps ? ad57 t samp sample time (1) 2.0 t ad ??? ? timing parameters ad60 t pcs conversion start from sample trigger (1) 2.0 t ad ? 3.0 t ad ? auto-convert trigger not selected ad61 t pss sample start from setting sample (samp) bit (1) 2.0 t ad ? 3.0 t ad ?? ad62 t css conversion completion to sample start (asam = 1 ) (1) ? 0.5 t ad ?? ? ad63 t dpu time to stabilize analog stage from adc off to adc on (1) ??20 s? note 1: these parameters are characterized but not tested in manufacturing. 2: because the sample caps will eventually lose charge, clock rates below 10 khz may affect linearity performance, especially at elevated temperatures. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 280 ? 2007-2012 microchip technology inc. notes: ? 2007-2012 microchip technology inc. ds70283k-page 281 dspic33fj32mc202/204 and dspic33fj16mc304 25.0 high temperature electrical characteristics this section provides an overview of dspic33fj32mc202 /204 and dspic33fj16mc304 electrical characteristics for devices operating in an ambient temperature range of -40c to +150c. the specifications between -40c to + 150c are identical to those shown in section 24.0 ?electri cal characteristics? for operation between -40c to +125c, with the exc eption of the parameters listed in this section. parameters in this section begin with an h, which den otes high temperature. for example, parameter dc10 in section 24.0 ?electrical characteristics? is the industrial and extended temperature equivalent of hdc10. absolute maximum ratings for the dspic33fj32mc202/2 04 and dspic33fj16mc304 high temperature devices are listed below. exposure to these maximum rating conditions for extended periods can affect device reliability. functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. absolute maximum ratings (1) ambient temperature under bias (4) .........................................................................................................-40c to +150c storage temperature ............................................................................................................ .................. -65c to +160c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant with respect to v ss (5) .................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd < 3.0v (5) .................................................... -0.3v to 3.6v voltage on any 5v tolerant pin with respect to v ss when v dd 3.0v (5) .................................................... -0.3v to 5.6v maximum current out of v ss pin ........................................................................................................................... ..60 ma maximum current into v dd pin (2) .............................................................................................................................60 ma maximum junction temperature...... ............................................................................................. .......................... +155c maximum current sourced/sunk by any 2x i/o pin (3) ................................................................................................2 ma maximum current sourced/sunk by any 4x i/o pin (3) ................................................................................................4 ma maximum current sourced/sunk by any 8x i/o pin (3) ................................................................................................8 ma maximum current sunk by all ports combined ........... ......................................................................... ....................70 ma maximum current sourced by all ports combined (2) ................................................................................................70 ma note 1: stresses above those listed under ?absolute maxi mum ratings? can cause permanent damage to the device. this is a stress rating only, and functional o peration of the device at th ose or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods can affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 25-2 ). 3: unlike devices at 125c and below, the specifications in this sect ion also apply to the clkout, v ref +, v ref -, sclx, sdax, pgcx and pgdx pins. 4: aec-q100 reliability testing for devices intended to operate at 150c is 1,000 hours. any design in which the total operating time from 125c to 150c will be greater than 1,000 hours is not warranted without prior written approval from microchip technology inc. 5: refer to the ? pin diagrams ? section for 5v tolerant pins. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 282 ? 2007-2012 microchip technology inc. 25.1 high temperature dc characteristics table 25-1: operating mips vs. voltage table 25-2: thermal operating conditions table 25-3: dc temperature and voltage specifications characteristic v dd range (in volts) temperature range (in c) max mips dspic33fj32mc202/204 and dspic33fj16mc304 hdc5 v bor to 3.6v (1) -40c to +150c 20 note 1: device is functional at v bormin < v dd < v ddmin . analog modules such as the adc will have degraded performance. device functionality is tested but not characterized. refer to parameter bo10 in ta b l e 2 4 - 11 for the minimum and maximum bor values. rating symbol min typ max unit high temperature devices operating junction temperature range t j -40 ? +155 c operating ambient temperature range t a -40 ? +150 c power dissipation: internal chip power dissipation: p int = v dd x (i dd - i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ({v dd - v oh } x i oh ) + (v ol x i ol ) maximum allowed power dissipation p dmax (t j - t a )/ ja w dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature parameter no. symbol characteristic min typ max units conditions operating voltage hdc10 supply voltage v dd ? 3.0 3.3 3.6 v -40c to +150c ? 2007-2012 microchip technology inc. ds70283k-page 283 dspic33fj32mc202/204 and dspic33fj16mc304 table 25-4: dc characteristics: power-down current (i pd ) table 25-5: dc characteristics: operating current (i dd ) table 25-6: dc characteristics: doze current (i doze ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature parameter no. typical max units conditions power-down current (i pd ) hdc60e 250 2000 a +150c 3.3v base power-down current (1,3) hdc61c 3 5 a +150c 3.3v watchdog timer current: i wdt (2,4) note 1: base i pd is measured with all peripheral s and clocks shut down. all i/os are configured as inputs and pulled to v ss . wdt, etc., are all switched off, and vregs (rcon<8>) = 1 . 2: the current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 3: these currents are measured on the device c ontaining the most memory in this family. 4: these parameters are characterized, but are not tested in manufacturing. dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature parameter no. typical (1) max units conditions hdc20 19 35 ma +150c 3.3v 10 mips hdc21 27 45 ma +150c 3.3v 16 mips hdc22 33 55 ma +150c 3.3v 20 mips note 1: these parameters are characterized, but are not tested in manufacturing. dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature parameter no. typical (1) max doze ratio units conditions hdc72a 39 45 1:2 ma +150c 3.3v 20 mips hdc72f 18 25 1:64 ma hdc72g 18 25 1:128 ma note 1: parameters with doze ratios of 1:2 and 1:64 are c haracterized, but are not tested in manufacturing. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 284 ? 2007-2012 microchip technology inc. table 25-7: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param. symbol characteristic mi n. typ. max. units conditions do10 v ol output low voltage i/o pins: 2x sink driver pins - all pins not defined by 4x or 8x driver pins ??0.4v i ol 1.8 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 4x sink driver pins - ra0, ra1, rb5, rb6, rb8, rb9, rb14 ??0.4v i ol 3.6 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 8x sink driver pins - osco, clko, ra3 ??0.4v i ol 6 ma, v dd = 3.3v see note 1 do20 v oh output high voltage i/o pins: 2x source driver pins - all pins not defined by 4x or 8x driver pins 2.4 ? ? v i ol -1.8 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 4x source driver pins - ra0, ra1, rb5, rb6, rb8, rb9, rb14 2.4 ? ? v i ol -3 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 8x source driver pins - osco, clko, ra3 2.4 ? ? v i ol -6 ma, v dd = 3.3v see note 1 do20a v oh 1 output high voltage i/o pins: 2x source driver pins - all pins not defined by 4x or 8x driver pins 1.5 ? ? v i oh -1.9 ma, v dd = 3.3v see note 1 2.0 ? ? i oh -1.85 ma, v dd = 3.3v see note 1 3.0 ? ? i oh -1.4 ma, v dd = 3.3v see note 1 output high voltage 4x source driver pins - ra0, ra1, rb5, rb6, rb8, rb9, rb14 1.5 ? ? v i oh -3.9 ma, v dd = 3.3v see note 1 2.0 ? ? i oh -3.7 ma, v dd = 3.3v see note 1 3.0 ? ? i oh -2 ma, v dd = 3.3v see note 1 output high voltage 8x source driver pins -osco, clko, ra3 1.5 ? ? v i oh -7.5 ma, v dd = 3.3v see note 1 2.0 ? ? i oh -6.8 ma, v dd = 3.3v see note 1 3.0 ? ? i oh -3 ma, v dd = 3.3v see note 1 note 1: parameters are characterized, but not tested. ? 2007-2012 microchip technology inc. ds70283k-page 285 dspic33fj32mc202/204 and dspic33fj16mc304 25.2 ac characteristics and timing parameters the information contained in this section defines dspic33fj32mc202/204 and dspic33fj16mc304 ac characteristics and timing parameters for high temperature devices. however, all ac timing specifications in this sect ion are the same as those in section 24.2 ?ac charac teristics and timing parameters? , with the exception of the parameters listed in this section. parameters in this section begin with an h, which denotes high temper ature. for example, parameter os53 in section 24.2 ?ac characteristics and timing parameters? is the industrial and extended temperature equivalent of hos53. table 25-8: temperature and voltage specifications ? ac figure 25-1: load conditions for device timing specifications table 25-9: pll clock timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature operating voltage v dd range as described in table 25-1 . ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic mi n typ max units conditions hos53 d clk clko stability (jitter) (1) -5 0.5 5 % measured over 100 ms period note 1: these parameters are characterized by similarity, but are not tested in manufacturing. this specification is based on clock cycle by clock cycle measurements. to ca lculate the effective jitt er for individual time bases or communication clocks use this formula: v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 ? for all pins except osc2 load condition 2 ? for osc2 peripheral clock jitter d clk f osc peripheral bit rate clock -------------------------------------------------------------- ?? ?? ----------------------------------------------------------------------- - = for example: fosc = 32 mhz, d clk = 5%, spi bit rate clock, (i.e., sck) is 2 mhz. spi sck jitter d clk 32 mhz 2 mhz -------------------- ?? ?? ------------------------------ 5% 16 --------- - 5% 4 ------- - 1.25% ==== dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 286 ? 2007-2012 microchip technology inc. table 25-10: spix master mode (cke = 0 ) timing requirements table 25-11: spix module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic (1) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?1025ns ? hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 28 ? ? ns ? hsp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 35 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic (1) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ?1025ns ? hsp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 35 ? ? ns ? hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 28 ? ? ns ? hsp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 35 ? ? ns ? note 1: these parameters are characterized but not tested in manufacturing. ? 2007-2012 microchip technology inc. ds70283k-page 287 dspic33fj32mc202/204 and dspic33fj16mc304 table 25-12: spix module slave mode (cke = 0 ) timing requirements table 25-13: spix module slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic (1) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ??35ns ? hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 25 ? ? ns ? hsp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 25 ? ? ns ? hsp51 tssh2doz ssx to sdox output high-impedance 15 ? 55 ns see note 2 note 1: these parameters are characterized but not tested in manufacturing. 2: assumes 50 pf load on all spix pins. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic (1) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge ? ? 35 ns ? hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 25 ? ? ns ? hsp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 25 ? ? ns ? hsp51 tssh2doz ssx to sdo x output high-impedance 15 ? 55 ns see note 2 hsp60 tssl2dov sdox data output valid after ssx edge ? ? 55 ns ? note 1: these parameters are characterized but not tested in manufacturing. 2: assumes 50 pf load on all spix pins. table 25-14: internal rc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for extended param no. characteristic min typ max units conditions lprc @ 32.768 khz (1,2) hf21 lprc -70 ? +70 % -40c t a +150c v dd = 3.0-3.6v note 1: change of lprc frequency as v dd changes. 2: lprc accuracy impacts the watchdog timer time-out period (t wdt 1). see section 21.4 ?watchdog timer (wdt)? for more information. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 288 ? 2007-2012 microchip technology inc. table 25-15: adc module specifications table 25-16: adc module specifications (12-bit mode) (3) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic min typ max units conditions reference inputs had08 i ref current drain ? ? 250 ? 600 50 a a adc operating, see note 1 adc off, see note 1 note 1: these parameters are not characterized or tested in manufacturing. 2: these parameters are characterized, but are not tested in manufacturing. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic min typ max units conditions adc accuracy (12-bit mode) ? measurements with external v ref +/v ref - (1) had20a nr resolution (3) 12 data bits bits ? had21a inl integral nonlinearity -2 ? +2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had22a dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had23a g err gain error -2 ? 10 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had24a e off offset error -3 ? 4 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v adc accuracy (12-bit mode) ? measurements with internal v ref +/v ref - (1) had20a nr resolution (3) 12 data bits bits ? had21a inl integral nonlinearity -2 ? +2 lsb v inl = av ss = 0v, av dd = 3.6v had22a dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 3.6v had23a g err gain error 2 ? 20 lsb v inl = av ss = 0v, av dd = 3.6v had24a e off offset error 2 ? 10 lsb v inl = av ss = 0v, av dd = 3.6v dynamic performance (12-bit mode) (2) had33a f nyq input signal bandwidth ? ? 200 khz ? note 1: these parameters are characterized, but are tested at 20 ksps only. 2: these parameters are characterized by simila rity, but are not tested in manufacturing. 3: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. ? 2007-2012 microchip technology inc. ds70283k-page 289 dspic33fj32mc202/204 and dspic33fj16mc304 table 25-17: adc module specifications (10-bit mode) (3) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic mi n typ max units conditions adc accuracy (10-bit mode) ? measurements with external v ref +/v ref - (1) had20b nr resolution (3) 10 data bits bits ? had21b inl integral nonlinearity -3 ? 3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had22b dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had23b g err gain error -5 ? 6 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had24b e off offset error -1 ? 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v adc accuracy (10-bit mode) ? measurements with internal v ref +/v ref - (1) had20b nr resolution (3) 10 data bits bits ? had21b inl integral nonlinearity -2 ? 2 lsb v inl = av ss = 0v, av dd = 3.6v had22b dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, av dd = 3.6v had23b g err gain error -5 ? 15 lsb v inl = av ss = 0v, av dd = 3.6v had24b e off offset error -1.5 ? 7 lsb v inl = av ss = 0v, av dd = 3.6v dynamic performance (10-bit mode) (2) had33b f nyq input signal bandwidth ? ? 400 khz ? note 1: these parameters are characterized, but are tested at 20 ksps only. 2: these parameters are characterized by simila rity, but are not tested in manufacturing. 3: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 290 ? 2007-2012 microchip technology inc. table 25-18: adc conversion (12- bit mode) timing requirements table 25-19: adc conversion (10- bit mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic min typ max units conditions clock parameters had50 t ad adc clock period (1) 147 ? ? ns ? conversion rate had56 f cnv throughput rate (1) ? ? 400 ksps ? note 1: these parameters are characterized but not tested in manufacturing. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic min typ max units conditions clock parameters had50 t ad adc clock period (1) 104 ? ? ns ? conversion rate had56 f cnv throughput rate (1) ??800ksps ? note 1: these parameters are characterized but not tested in manufacturing. ? 2007-2012 microchip technology inc. ds70283k-page 291 dspic33fj32mc202/204 and dspic33fj16mc304 26.0 dc and ac device characteristics graphs figure 26-1: v oh ? 2x driver pins figure 26-2: v oh ? 4x driver pins figure 26-3: v oh ? 8x driver pins figure 26-4: v oh ? 16x driver pins note: the graphs provided following this note ar e a statistical summary based on a limited num ber of samples and are provided for des ign guidance purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs, the data presented may be outside t he specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. -0.016 -0.014 -0.012 -0.010 -0.008 -0.006 -0.004 ioh (a) -0.016 -0.014 -0.012 -0.010 -0.008 -0.006 -0.004 -0.002 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh (a) voh (v) 3v 3.3v 3.6v -0.030 -0.025 -0.020 -0.015 -0.010 ioh (a) -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh (a) voh (v) 3v 3.3v 3.6v -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 ioh (a) -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 1.00 2.00 3.00 4.00 ioh (a) voh (v) 3v 3.3v 3.6v -0.080 -0.070 -0.060 -0.050 -0.040 -0.030 -0.020 ioh (a) -0.080 -0.070 -0.060 -0.050 -0.040 -0.030 -0.020 -0.010 0.000 0.00 1.00 2.00 3.00 4.00 ioh (a) voh (v) 3v 3.3v 3.6v dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 292 ? 2007-2012 microchip technology inc. figure 26-5: v ol ? 2x driver pins figure 26-6: v ol ? 4x driver pins figure 26-7: v ol ? 8x driver pins figure 26-8: v ol ? 16x driver pins 0.006 0.008 0.010 0.012 0.014 0.016 0.018 0.020 iol (a) 0.000 0.002 0.004 0.006 0.008 0.010 0.012 0.014 0.016 0.018 0.020 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v 0.010 0.015 0.020 0.025 0.030 0.035 0.040 iol (a) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v 0.020 0.030 0.040 0.050 0.060 iol (a) 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v 0.040 0.060 0.080 0.100 0.120 iol (a) 0.000 0.020 0.040 0.060 0.080 0.100 0.120 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v ? 2007-2012 microchip technology inc. ds70283k-page 293 dspic33fj32mc202/204 and dspic33fj16mc304 figure 26-9: typical i pd current @ v dd = 3.3v, +85oc figure 26-10: typical i dd current @ v dd = 3.3v, +85oc figure 26-11: typical i doze current @ v dd = 3.3v, +85oc figure 26-12: typical i idle current @ v dd = 3.3v, +85oc 200 300 400 500 600 700 ipd current [a] 0 100 200 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature celsius 20 30 40 50 60 average (ma) 0 10 0 102030405060 f cy (mips) pmd = 0, no pll pmd = 0, with pll 20.00 30.00 40.00 50.00 60.00 current (ma) 0.00 10.00 1:1 1:2 1:64 1:128 doze ratio 10 15 20 25 l e current (ma) 0 5 0 10203040 i id l mips dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 294 ? 2007-2012 microchip technology inc. figure 26-13: typical frc frequency @ v dd = 3.3v figure 26-14: typical lprc frequency @ v dd = 3.3v 7450 7350 7400 7300 7350 n cy (khz) 7200 7250 freque n 7150 7100 -40-30-20-10 0 102030405060708090100110120 temperature celsius 35 29 31 33 z) 25 27 29 uency (kh 21 23 l prc freq 17 19 l 15 -40-30-20-10 0 102030405060708090100110120 temperature celsius ? 2007-2012 microchip technology inc. ds70283k-page 295 dspic33fj32mc202/204 and dspic33fj16mc304 27.0 packaging information 27.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note: if the full microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead spdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example dspic33fj32mc 0730235 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example dspic33fj32mc 0730235 202-e/sp 202-e/so 3 e 3 e 28-lead ssop xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example 33fj32mc 202-e/ss 0730235 3 e dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 296 ? 2007-2012 microchip technology inc. 27.1 package marking information (continued) legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note: if the full microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead qfn-s xxxxxxxx xxxxxxxx yywwnnn example 33fj32mc 202e/mm 0730235 xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn dspic33fj32 example mc204-e/ml 0730235 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example dspic33fj 32mc204 0730235 -e/pt 3 e 3 e 3 e ? 2007-2012 microchip technology inc. ds70283k-page 297 dspic33fj32mc202/204 and dspic33fj16mc304 27.2 package details 28-lead skinny plastic dual in-line (sp) ? 300 mil body [spdip] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 28 pitch e .100 bsc top to seating plane a ? ? .200 molded package thickness a2 .120 .135 .150 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .335 molded package width e1 .240 .285 .295 overall length d 1.345 1.365 1.400 tip to seating plane l .110 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .050 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 note 1 n 12 d e1 e b c e l a2 e b b1 a1 a 3 microchip technology drawing c04-070b dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 298 ? 2007-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2007-2012 microchip technology inc. ds70283k-page 299 dspic33fj32mc202/204 and dspic33fj16mc304 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 300 ? 2007-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2007-2012 microchip technology inc. ds70283k-page 301 dspic33fj32mc202/204 and dspic33fj16mc304 ! " # $ % !" # $% &" ' ()"&'"!&) & #*&& & # ' !! #+#&"# '#% ! &"!! #% ! &"!!! & $ # '' !# , ' ! #& +- . /01 / !' ! & $ & " !**&"&& ! +21 % ' !("!" *&"&& (%%' & " ! ! $ % 2& '!&" & 3 # * !( ! ! & 3 % & & # & && 144*** ' '4 3 5&! 66 ++ ' !6'&! 7 78 9 7"') % ! 7 : & ./0 8 ; & < < # # 3 3 !! . . :. & #%% . < < 8 =#& + : : # # 3 =#& + . . , . 8 6 & . 2&6 & 6 .. . . 2& & 6 .+2 6 #3 !! < . 2& > > :> 6 #=#& ) < ,: l l1 c a2 a1 a e e1 d n 1 2 note 1 b e * 0 ,/ dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 302 ? 2007-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2007-2012 microchip technology inc. ds70283k-page 303 dspic33fj32mc202/204 and dspic33fj16mc304 & ' ( $ ) ** +,+, - ! "&'$# . / 0 ) $ % !" # $% &" ' ()"&'"!&) & #*&& & # 3 !! *! " & # , ' ! #& +- . /01 / !' ! & $ & " !**&"&& ! +21 % ' !("!" *&"&& (%%' & " ! ! $ % 2& '!&" & 3 # * !( ! ! & 3 % & & # & && 144*** ' '4 3 5&! 66 ++ ' !6'&! 7 78 9 7"') % ! 7 : & ./0 8 ; & : & #%% . 0& &3 !! , +2 8 =#& + /0 +$ ! # #=#& + , . , 8 6 & /0 +$ ! # #6 & , . , 0& &=#& ) , ,: , 0& &6 & 6 , . 0& & & +$ ! # # ? < < d e 2 1 n e2 exposed pad 2 1 d2 n e b k l note 1 a3 a a1 top view bottom view * 0 / dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 304 ? 2007-2012 microchip technology inc. & ' ( $ ) ** +,+, - ! "&'$# . / 0 ) $ % 2& '!&" & 3 # * !( ! ! & 3 % & & # & && 144*** ' '4 3 ? 2007-2012 microchip technology inc. ds70283k-page 305 dspic33fj32mc202/204 and dspic33fj16mc304 44-lead plastic quad flat, no lead package (ml) C 8x8 mm body [qfn] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package is saw singulated. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 44 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 8.00 bsc exposed pad width e2 6.30 6.45 6.80 overall length d 8.00 bsc exposed pad length d2 6.30 6.45 6.80 contact width b 0.25 0.30 0.38 contact length l 0.30 0.40 0.50 contact-to-exposed pad k 0.20 C C d exposed pad d2 e b k l e2 2 1 n note 1 2 1 e n b otto m view to p view a3 a1 a microchip technology drawing c04-103b dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 306 ? 2007-2012 microchip technology inc. // & ' ( $ ) * , ! "&'$# $ % 2& '!&" & 3 # * !( ! ! & 3 % & & # & && 144*** ' '4 3 ? 2007-2012 microchip technology inc. ds70283k-page 307 dspic33fj32mc202/204 and dspic33fj16mc304 44-lead plastic t hin quad flatpack (p t ) C 10x10x1 mm body, 2.00 mm footprint [ t qfp] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. chamfers at corners are optional; size may vary. 3. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.25 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of leads n 44 lead pitch e 0.80 bsc overall height a C C 1.20 molded package thickness a2 0.95 1.00 1.05 standoff a1 0.05 C 0.15 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 3.5 7 overall width e 12.00 bsc overall length d 12.00 bsc molded package width e1 10.00 bsc molded package length d1 10.00 bsc lead thickness c 0.09 C 0.20 lead width b 0.30 0.37 0.45 mold draft angle top 11 12 13 mold draft angle bottom 11 12 13 a e e1 d d1 e b note 1 note 2 n 123 c a1 l a2 l1 microchip technology drawing c04-076b dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 308 ? 2007-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2007-2012 microchip technology inc. ds70283k-page 309 dspic33fj32mc202/204 and dspic33fj16mc304 appendix a: revision history revision a (february 2007) this is the initial releas ed version of the document. revision b (may 2007) this revision includes the following corrections and updates: ? minor typographical and formatting corrections throughout the data sheet text. ? new content: - addition of bullet item (16-word conversion result buffer) (see section 20.1 ?key features? ) ? updated register map information for rpinr14 and rpinr15 (see table 4-16) ? figure updates: - updated oscillator system diagram (see figure 8-1) - updated wdt block diagram (see figure 21-2) ? equation update: - serial clock rate (see equation 17-1) ? register updates: - peripheral pin select input registers (see register 10-1 through register 10-13) - updated adc1 input channel 0 select register (see register 20-5) ? the following tables in section 24.0 ?electrical characteristics? have been updated with preliminary values: - updated max mips for -40c to +125c temp range (see table 24-1) - updated parameter dc18 (see table 24-4) - added new parameters for +125c, and updated typical and max values for most parameters (see table 24-5) - added new parameters for +125c, and updated typical and max values for most parameters (see table 24-6) - added new parameters for +125c, and updated typical and max values for most parameters (see table 24-7) - added new parameters for +125c, and updated typical and max values for most parameters (see table 24-8) - updated parameter di51, added parameters di51a, di51b, and di51c (see table 24-9) - added note 1 (see table 24-11) - updated parameters os10 and os30 (see table 24-16) - updated parameter os52 (see table 24-17) - updated parameter f20, added note 2 (see table 24-18) - updated parameter f21 (see table 24-19) - updated parameter ta15 (see table 24-22) - updated parameter tb15 (see table 24-23) - updated parameter tc15 (see table 24-24) - updated parameter ic15 (see table 24-26) - updated parameters ad05, ad06, ad07, ad08, ad10 through ad13 and ad17; added parameters ad05a and ad06a; added note 2; modified adc accuracy headings to include measurement information (see table 24-38) - separated the adc module specifications table into three tables (see table 24-38, table 24-39, and table 24-40) - updated parameter ad50 (see table 24-41) - updated parameters ad50 and ad57 (see table 24-42) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 310 ? 2007-2012 microchip technology inc. revision c (june 2008) this revision includes minor typographical and formatting changes throughout the data sheet text. the major changes are referenced by their respective section in the following table. table a-1: major section updates section name update description ?high-performance, 16-bit digital signal controllers? added extended interrupts column to remappable peripherals in the controller families table and note 3 (see table 1). added note 1 to all pin diagrams, which references rpn pin usage by remappable peripherals (see ?pin diagrams? ). section 1.0 ?device overview? changed porta pin name from ra15 to ra10 (see table 1-1). section 4.0 ?memory organization? added sfr definitions (accal, acca h, accau, accbl, accbh, and accbu) to the cpu core register map (see table 4-1). updated reset value for corcon (see table 4-1). updated reset values for the followin g sfrs: ipc1, ipc3-ipc5, ipc7, ipc16, and inttreg (see table 4-4). updated all sfr names in qei1 register map (see table 4-10). updated the bit range for ad1con3 from adcs< 5 :0> to adcs< 7 :0>) (see table 4-14 and table 4-15). updated the reset value for clkdiv in the system control register map (see table 4-23). section 6.0 ?resets? entire section was replac ed to maintain consistency with other dspic33f data sheets. section 8.0 ?oscillator configuration? removed the first sentence of the third cl ock source item (external clock) in section 8.1.1.2 ?primary? . updated the default bit values for do ze and frcdiv in the clock divisor register (see register 8-2). added the center frequency in the osctun register for the frc tuning bits (tun<5:0>) value 011111 and updated the center frequency for bits value 011110 (see register 8-4). section 9.0 ?power-saving features? added the following two registers: ? pmd1: peripheral module disable control register 1 ? pmd2: peripheral module disable control register 2 ? pmd3: peripheral module disable control register 3 section 10.0 ?i/o ports? added paragraph and table 10-1 to section 10.2 ?open-drain configuration? , which provides details on i/o pins and their functionality. removed the following sections, which are now available in the related section of the dspic33f/pic24 h family reference manual: ? 9.4.2 ?available peripherals? ? 9.4.3.3 ?mapping? ? 9.4.5 ?considerations for peripheral pin selection? section 14.0 ?output compare? replaced sections 13.1, 13.2, and 13. 3 and related figures and tables with entirely new content. ? 2007-2012 microchip technology inc. ds70283k-page 311 dspic33fj32mc202/204 and dspic33fj16mc304 section 15.0 ?motor control pwm module? removed the following sections, which are now available in the related section of the dspic33f/pic24 h family reference manual: ? 14.3 ?pwm time base? ? 14.4 ?pwm period? ? 14.5 ?edge-aligned pwm? ? 14.6 ?center-aligned pwm? ? 14.7 ?pwm duty cycle comparison units? ? 14.8 ?complementary pwm operation? ? 14.9 ?dead-time generators? ? 14.10 ?independent pwm output? ? 14.11 ?single pulse pwm operation? ? 14.12 ?pwm output override? ? 14.13 ?pwm output and polarity control? ? 14.14 ?pwm fault pins? ? 14.15 ?pwm update lockout? ? 14.16 ?pwm special event trigger? ? 14.17 ?pwm operation during cpu sleep mode? ? 14.18 ?pwm operation during cpu idle mode? section 16.0 ?quadrature encoder interface (q ei) module? removed the following sections, which are now available in the related section of the dspic33f/pic24 h family reference manual: ? 15.1 ?quadrature encoder interface logic? ? 15.2 ?16-bit up/down position counter mode? ? 15.3 ?position measurement mode? ? 15.4 ?programmable digital noise filters? ? 15.5 ?alternate 16-bit timer/counter? ? 15.6 qei module operation during cpu sleep mode? ? 15.7 ?qei module operation during cpu idle mode? ? 15.8 ?quadrature encode r interface interrupts? section 17.0 ?serial peripheral interface (spi)? removed the following sections, which are now available in the related section of the dspic33f/pic24 h family reference manual: ? 16.1 ?interrupts? ? 16.2 ?receive operations? ? 16.3 ?transmit operations? ? 16.4 ?spi setup? (retained figure 1 7-1: spi module block diagram) table a-1: major section updates (continued) section name update description dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 312 ? 2007-2012 microchip technology inc. section 18.0 ?inter-integrated circuit? (i2c?)? removed the following sections, which are now available in the related section of the dspic33f/pic24 h family reference manual: ? 17.3 ?i 2 c interrupts? ? 17.4 ?baud rate generator? (retained figure 15-1: i 2 c block diagram) ? 17.5 ?i 2 c module addresses? ? 17.6 ?slave address masking? ? 17.7 ?ipmi support? ? 17.8 ?general call address support? ? 17.9 ?automatic clock stretch? ? 17.10 ?software controlled clock stretching (stren = 1 )? ? 17.11 ?slope control? ? 17.12 ?clock arbitration? ? 17.13 ?multi-master communication, bus collision, and bus arbitration? ? 17.14 ?peripheral pin select limitations? section 19.0 ?universal asynchronous receiver transmitter (uart)? removed the following sections, which are now available in the related section of the dspic33f/pic24 h family reference manual: ? 18.1 ?uart baud rate generator? ? 18.2 ?transmitting in 8-bit data mode? ? 18.3 ?transmitting in 9-bit data mode? ? 18.4 ?break and sync transmit sequence? ? 18.5 ?receiving in 8-bit or 9-bit data mode? ? 18.6 ?flow control using uxcts and uxrts pins? ? 18.7 ?infrared support? removed irda references and note 1, and updated the bit and bit value descriptions for utxinv (uxsta<14>) in the uartx status and control register (see register 19-2). section 20.0 ?10-bit/12-bit analog-to-digital converter (adc)? removed equation 19-1: adc conversion clock period and figure 19-2: adc transfer function (10-bit example). added adc1 module block diagram for dspic33fj16mc304 and dspic33fj32mc204 devices (figure 20-1) and adc1 module block diagram for dspic33fj32mc202 devices (figure 20-2). added note 2 to figure 20-3: adc conversion clock period block diagram. updated adc conversion clock select bits in the ad1con3 register from adcs< 5 :0> to adcs< 7 :0>. any references to these bits have also been updated throughout this data sheet (register 20-3). added device-specific information to no te 1 in the adc1 input scan select register low (see register 20-6), and updated the default bit value for bits 12-10 (css12-css10) from u-0 to r/w-0. added device-specific information to no te 1 in the adc1 port configuration register low (see register 20-7), and updated the default bit value for bits 12-10 (pcfg12-pcfg10) from u-0 to r/w-0. table a-1: major section updates (continued) section name update description ? 2007-2012 microchip technology inc. ds70283k-page 313 dspic33fj32mc202/204 and dspic33fj16mc304 section 21.0 ?special features? added ficd register information fo r address 0xf8000e in the device configuration register map (see table 21-1). added ficd register content (bkbug, coe, jtagen, and ics<1:0> to the dspic33fj32mc202/204 and dspic33f j16mc304 configuration bits description (see table 21-2). added a note regarding the placement of low-esr capacitors, after the second paragraph of section 21.2 ?on-chip voltage regulator? and to figure 19-1. removed the words ?if enabled? from the second sentence in the fifth paragraph of section 21.3 ?bor: brown-out reset? . section 24.0 ?electrical characteristics? updated max mips value for -40oc to +125oc temperature range in operating mips vs. voltage (see table 24-1). removed typ value for parameter dc12 (see table 24-4). updated mips conditions for para meters dc24c, dc44c, dc72a, dc72f and dc72g (see table 24-5, table 24-6, and table 24-8). added note 4 (reference to new table containing digital-only and analog pin information to i/o pin input sp ecifications (see table 24-4). updated typ, min and max values for program memory parameters d136, d137 and d138 (see table 24-12). updated max value for internal rc accuracy parameter f21 for -40c t a +125c condition and added note 2 (see table 24-19). removed all values for reset, watchdog timer, oscillator start-up timer, and power-up timer parameter sy20 and updated conditions, which now refers to section 21.4 ?watchdog timer (wdt)? and lprc parameter f21a (see table 24-21). updated min and typ values for parameters ad60, ad61, ad62 and ad63 and removed note 3 (see table 24-41). updated min and typ values for parameters ad60, ad61, ad62 and ad63 and removed note 3 (see table 24-42). table a-1: major section updates (continued) section name update description dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 314 ? 2007-2012 microchip technology inc. revision d (december 2008) this revision includes minor typographical and formatting changes throughout the data sheet text. the major changes are referenced by their respective section in the following table. table a-2: major section updates section name update description ?high-performance, 16-bit digital signal controllers? updated all pin diagrams to denote the pin voltage tolerance (see ?pin diagrams? ). section 2.0 ?guidelines for getting started with 16-bit digital signal controllers? added new section to the data sheet t hat provides guidelines on getting started with 16-bit digital signal controllers. section 10.0 ?i/o ports? updated 5v tolerant status for i/o pin rb4 from yes to no (see table 10-1). section 24.0 ?electrical characteristics? removed the maximum value for para meter dc12 (ram data retention voltage) in table 24-4. updated typical values for operating current (i dd ) and added note 3 in table 24-5. updated typical and maximum values for idle current (i idle ): core off clock on base current and added note 3 in table 24-6. updated typical and maximum values for power down current (i pd ) and added note 5 in table 24-7. updated typical and maximum values for doze current (id oze ) and added note 2 in table 24-8. added note 3 to table 24-12. updated minimum value for internal voltage regulator specifications in table 24-13. added parameter os42 (g m ) and notes 4, 5 and 6 to table 24-16. added notes 2 and 3 to table 24-17. added note 2 to table 24-20. added note 2 to table 24-21. added note 2 to table 24-22. added note 1 to table 24-23. added note 1 to table 24-24. added note 3 to table 24-36. added note 2 to table 24-37. updated typical value for parameter ad08 (adc in operation) and added notes 2 and 3 in table 24-38. updated minimum, typical, and maximum values for parameters ad23a, ad24a, ad30a, ad32a, ad32a and ad34a, and added notes 2 and 3 in table 24-39. updated minimum, typical, and maximum values for parameters ad23b, ad24b, ad30b, ad32b, ad32b and ad34b, and added notes 2 and 3 in table 24-40. ? 2007-2012 microchip technology inc. ds70283k-page 315 dspic33fj32mc202/204 and dspic33fj16mc304 revision e (june 2009) this revision includes minor typographical and formatting changes throughout the data sheet text. global changes include: ? changed all instances of osci to osc1 and osco to osc2 ? changed all instances of pgcx/emucx and pgdx/emudx (where x = 1, 2 or 3) to pgecx and pgedx changed all instances of v ddcore and v ddcore /v cap to v cap /v ddcore all other major changes are referenced by their respective section in the following table. table a-3: major section updates section name update description ?high-performance, 16-bit digital signal controllers? added note 2 to the 28-pin qfn-s and 44-pin qfn pin diagrams, which references pin connections to v ss . section 7.0 ?inte rrupt controller? updated addresses for interrupt vectors 80, 81, 82 and 83-125 (see table 7-1). section 8.0 ?oscillator configuration? updated the oscillator system diagram (see figure 8-1). added note 1 to the oscillator tuning register (osctun) (see register 8-4). section 10.0 ?i/o ports? removed table 10-1 and added reference to pin diagrams for i/o pin availability and functionality. section 17.0 ?serial peripheral interface (spi)? added note 2 to the spix control register 1 (see register 17-2). section 19.0 ?universal asynchronous receiver transm itter (uart)? updated the utxinv bit settings in the uxsta register and added note 1 (see register 19-2). section 24.0 ?electrical characteristics? updated the min value for parameter dc12 (ram retention voltage) and added note 4 to the dc temperature and voltage specifications (see table 24-4). updated the min value for parameter di35 (see table 24-20). updated ad08 and added reference to note 2 for parameters ad05a, ad06a and ad08a (see table 24-38). dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 316 ? 2007-2012 microchip technology inc. revision f (november 2009) the revision includes the following global update: ? added note 2 to the shaded table that appears at the beginning of each chapter. this new note provides information regarding the availability of registers and their associated bits this revision also includes minor typographical and formatting changes throughout the data sheet text. all other major changes are referenced by their respective section in the following table. revision g (november 2009) this revision includes minor typographical and formatting changes throughout the data sheet text. all other major changes are referenced by their respective section in the following table. table a-4: major section updates section name update description ?high-performance, 16-bit digital signal controllers? added information on high temperature operation (see ?operating range:? ). section 10.0 ?i/o ports? changed the reference to digital-only pins to 5v tolerant pins in the second paragraph of section 10.2 ?open-drain configuration? . section 19.0 ?universal asynchronous receiver transmitter (uart)? updated the two baud rate range features to: 10 mbps to 38 bps at 40 mips. section 20.0 ?10-bit/12-bit analog-to-digital converter (adc)? updated the adc1 block diagrams (see figure 20-1 and figure 20-2). section 21.0 ?special features? updated the second paragraph and removed the fourth paragraph in section 21.1 ?configuration bits? . updated the device configurati on register map (see table 21-1). section 24.0 ?electrical characteristics? updated the absolute maximum ratings for high temperature and added note 4. updated the spix module slave mode (cke = 1 ) timing characteristics (see figure 24-17). updated the internal rc accuracy parameter numbers (see table 24-18 and table 24-19). section 25.0 ?high temperature electrical characteristics? added new chapter with high temperature specifications. ?product identification system? added the ?h? definition for high temperature. table a-5: major section updates section name update description section 25.0 ?high temperature electrical characteristics? updated mips rating from 16 to 20 for high temperature devices in ?operating range:? and in table 25-1: operating mips vs. voltage. ? 2007-2012 microchip technology inc. ds70283k-page 317 dspic33fj32mc202/204 and dspic33fj16mc304 revision h (february 2011) this revision includes typographical and formatting changes throughout the data s heet text. in addition, all instances of v ddcore have been removed. all other major changes are referenced by their respective section in the following table. table a-6: major section updates section name update description high-performance, 16-bit digital signal controllers added the ssop package information (see ?packaging:? , table 1, and ?pin diagrams? ). section 2.0 ?guidelines for getting started with 16-bit digital signal controllers? updated the title of section 2.3 ?cpu logic filter capacitor connection (v cap )? . the frequency limitation for device pll start-up conditions was updated in section 2.7 ?oscillator valu e conditions on device start-up? . the second paragraph in section 2.9 ?unused i/os? was updated. section 3.0 ?cpu? removed references to dma in the cpu core block diagram (see figure 3-1). section 4.0 ?memory organization? updated the data memory reference in the third paragraph in section 4.2 ?data address space? . all resets values for the following sfrs in the timer register map were changed (see table 4-5): ?tmr1 ?tmr2 ?tmr3 section 8.0 ?oscillator configuration? added note 3 to the osccon: osci llator control register (see register 8-1). added note 2 to the clkdiv: clock divisor register (see register 8-2). added note 1 to the pllfbd: pll feedback divisor register (see register 8-3). added note 2 to the osctun: frc oscillator tuning register (see register 8-4). section 20.0 ?10-bit/12-b it analog-to-digital converter (adc)? updated the v refl references in the adc1 module block diagrams (see figure 20-1 and figure 20-2). section 21.0 ?special features? added a new paragraph and removed the third paragraph in section 21.1 ?configuration bits? . added the column ?rtsp effects? to the configuration bits descriptions (see table 21-2). dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 318 ? 2007-2012 microchip technology inc. section 24.0 ?electrical characteristics? added the 28-pin ssop thermal packaging characteristics (see table 24-3). removed note 4 from the dc temperature and voltage specifications (see table 24-4). updated the maximum value for parameter di19 and added parameters di28, di29, di60a, di60b , and di60c to the i/o pin input specifications (see table 24-9). updated note 3 of the pll clo ck timing specifications (see table 24-17). removed note 2 from the ac characteristics: internal rc accuracy (see table 24-18). updated the characteristic description for parameter di35 in the i/o timing requirements (see table 24-20). updated all spi specifications (s ee table 24-32 through table 24-39 and figure 24-14 through figure 24-21). added note 4 to the 12-bit mode adc module specifications (see table 24-43). added note 4 to the 10-bit mode adc module specifications (see table 24-44). section 25.0 ?high temperature electrical characteristics? updated all ambient temperatur e and range values to +150oc throughout the chapter. updated the storage temper ature and range to +160oc. updated the maximum junction tem perature from +145oc to +155oc. updated note 1 in the pll clock timing specifications (see table 25-10). added note 3 to the 12-bit mode adc module specifications (see table 25-17). added note 3 to the 10-bit mode adc module specifications (see table 25-18). section 26.0 ?packaging information? added the 28-lead ssop package information (see section 26.1 ?package marking information? and section 26.2 ?package details? ). ?product identification system? added the ?ss? definition for the ssop package. table a-6: major section updates (continued) section name update description ? 2007-2012 microchip technology inc. ds70283k-page 319 dspic33fj32mc202/204 and dspic33fj16mc304 revision j (july 2011) this revision includes typographical and formatting changes throughout the data sheet text. all other major changes are referenced by their respective section in the following table. revision k (june 2012) this revision includes typographical and formatting changes throughout the data sheet text. all other major changes are referenced by their respective section in the following table. table a-7: major section updates section name update description section 21.0 ?special features? added note 3 to the connections for the on-chip voltage regulator diagram (see figure 21-1). section 24.0 ?electrical characteristics? removed note 3 and parameter dc10 (v core ) from the dc temperature and voltage specifications (see table 24-4). updated the characteristics definition and conditions for parameter bo10 in the electrical characteristics: bor (see table 24-11 ). added note 1 to the internal volt age regulator specifications (see table 24-13). table a-8: major section updates section name update description section 24.0 ?electrical characteristics? added note 1 to the operat ing mips vs. voltage (see table 24-1 ). updated the notes in the following tables: ? operating current (i dd ) (see ta b l e 2 4 - 5 ) ? idle current (i idle ) (see table 24-6 ) ? power-down current (i pd ) (see ta b l e 2 4 - 7 ) ? doze current (i doze ) (see table 24-8 ) updated the conditions for program memory parameters d136b, d137b, and d138b (t a = +150oc) (see table 24-12 ). section 25.0 ?high temperature electrical characteristics? removed table 23-8: dc characteristics: program memory. section 26.0 ?dc and ac device characteristics graphs? added new chapter. dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 320 ? 2007-2012 microchip technology inc. notes: ? 2007-2012 microchip technology inc. ds70283k-page 321 dspic33fj32mc202/204 and dspic33fj16mc304 index a ac characteristics .................................................... 244, 285 adc module.............................................................. 288 adc module (10-bit mode) ....................................... 289 adc module (12-bit mode) ....................................... 288 internal rc accuracy ................................................ 246 load conditions ................................................ 244, 285 adc initialization ............................................................... 199 key features............................................................. 199 adc module adc1 register map for dspic33fj32mc202 ............ 40 adc1 register map for dspic33fj32mc204 and dspic33fj16mc304 .......................................... 41 alternate interrupt vector table (aivt) .............................. 71 analog-to-digital converter (adc).................................... 199 arithmetic logic unit (alu)................................................. 24 assembler mpasm assembler................................................... 228 b barrel shifter ....................................................................... 28 bit-reversed addressing .................................................... 49 example ...................................................................... 50 implementation ........................................................... 49 sequence table (16-entry)......................................... 50 block diagrams 16-bit timer1 module ................................................ 143 a/d module ....................................................... 200, 201 connections for on-chip voltage regulator............. 215 device clock ............................................................. 101 dsp engine ................................................................ 25 dspic33fj32mc202/204 and dspic33fj16mc304 .. 10 dspic33fj32mc202/204 and dspic33fj16mc304 cpu core ........................................................... 18 dspic33fj32mc202/204 and dspic33fj16mc304 pll 103 input capture ............................................................ 151 output compare ....................................................... 155 pll............................................................................ 103 pwm module .................................................... 160, 161 quadrature encoder interface .................................. 173 reset system.............................................................. 61 shared port structure ............................................... 117 spi ............................................................................ 179 timer2 (16-bit) .......................................................... 148 timer2/3 (32-bit) ....................................................... 148 uart ........................................................................ 193 watchdog timer (wdt) ............................................ 216 c c compilers mplab c18 .............................................................. 228 clock switching................................................................. 110 enabling .................................................................... 110 sequence.................................................................. 110 code examples erasing a program memory page............................... 59 initiating a programming sequence............................ 60 loading write buffers ................................................. 60 port write/read ........................................................ 118 pwrsav instruction syntax..................................... 111 code protection ........................................................ 211, 218 configuration bits.............................................................. 211 configuration register map .............................................. 211 configuring analog port pins............................................ 118 cpu control register.......................................................... 21 cpu clocking system ...................................................... 102 pll configuration..................................................... 102 selection................................................................... 102 sources .................................................................... 102 customer change notification service............................. 325 customer notification service .......................................... 325 customer support............................................................. 325 d data accumulators and adder/subtracter .......................... 26 data space write saturation ...................................... 28 overflow and saturation ............................................. 26 round logic ............................................................... 27 write back .................................................................. 27 data address space........................................................... 31 alignment.................................................................... 31 memory map for dspic33fj32mc202/204 and dspic33fj16mc304 devices with 2 kbs ram . 32 near data space ........................................................ 31 software stack ........................................................... 46 width .......................................................................... 31 dc and ac characteristics graphs and tables ................................................... 291 dc characteristics............................................................ 232 doze current (i doze )................................................ 283 high temperature..................................................... 282 i/o pin input specifications ...................................... 238 i/o pin output specifications............................ 241, 284 idle current (i doze ) .................................................. 237 idle current (i idle ) .................................................... 235 operating current (i dd ) ............................................ 234 operating mips vs. voltage ..................................... 282 power-down current (i pd )........................................ 236 power-down current (i pd ) ........................................ 283 program memory...................................................... 242 temperature and voltage......................................... 282 temperature and voltage specifications.................. 233 thermal operating conditions.................................. 282 development support ....................................................... 227 doze mode ....................................................................... 112 dsp engine ........................................................................ 24 multiplier ..................................................................... 26 e electrical characteristics .................................................. 231 ac..................................................................... 244, 285 equations device operating frequency.................................... 102 errata .................................................................................... 7 f fail-safe clock monitor .................................................... 110 flash program memory ...................................................... 55 control registers........................................................ 56 operations .................................................................. 56 programming algorithm.............................................. 59 rtsp operation ......................................................... 56 table instructions ....................................................... 55 flexible configuration ....................................................... 211 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 322 ? 2007-2012 microchip technology inc. h high temperature electrical characteristics..................... 281 i i/o ports ............................................................................ 117 parallel i/o (pio)....................................................... 117 write/read timing .................................................... 118 i 2 c addresses ................................................................. 187 operating modes ...................................................... 185 registers ................................................................... 187 software controlled clock stretching (stren = 1).. 187 i 2 c module i2c1 register map ...................................................... 39 in-circuit debugger ........................................................... 217 in-circuit emulation........................................................... 211 in-circuit serial programming (icsp) ....................... 211, 217 input capture .................................................................... 151 registers ................................................................... 153 input change notification.................................................. 118 instruction addressing modes............................................. 46 file register instructions ............................................ 46 fundamental modes supported.................................. 47 mac instructions......................................................... 47 mcu instructions ........................................................ 46 move and accumulator instructions ............................ 47 other instructions........................................................ 47 instruction set overview ................................................................... 222 summary................................................................... 219 instruction-based power-saving modes ........................... 111 idle ............................................................................ 112 sleep ......................................................................... 111 interfacing program and data memory spaces .................. 51 internal rc oscillator use with wdt ........................................................... 216 internet address................................................................ 325 interrupt control and status registers................................ 74 iecx ............................................................................ 74 ifsx............................................................................. 74 intcon1 .................................................................... 74 intcon2 .................................................................... 74 ipcx ............................................................................ 74 interrupt setup procedures ............................................... 100 initialization ............................................................... 100 interrupt disable........................................................ 100 interrupt service routine .......................................... 100 trap service routine ................................................ 100 interrupt vector table (ivt) ................................................ 71 interrupts coincident with power save instructions.......... 112 j jtag boundary scan interface ........................................ 211 jtag interface .................................................................. 217 m memory organization.......................................................... 29 microchip internet web site .............................................. 325 modulo addressing ............................................................. 48 applicability ................................................................. 49 operation example ..................................................... 48 start and end address ................................................ 48 w address register selection .................................... 48 motor control pwm........................................................... 159 motor control pwm module 2-output register map................................................ 38 6-output register map for dspic33fj12mc202........ 38 mplab asm30 assembler, linker, librarian ................... 228 mplab integrated development environment software.. 227 mplab pm3 device programmer .................................... 230 mplab real ice in-circuit emulator system ................ 229 mplink object linker/mplib object librarian ................ 228 n nvm module register map .............................................................. 45 o open-drain configuration................................................. 118 oscillator configuration .................................................... 101 output compare ............................................................... 155 p packaging ......................................................................... 295 details....................................................................... 297 marking ............................................................. 295, 296 peripheral module disable (pmd) .................................... 112 pinout i/o descriptions (table)............................................ 11 pmd module register map .............................................................. 45 porta register map for dspic33fj32mc202....................... 43 register map for dspic33fj32mc204 and dspic33fj16mc304 .......................................... 43 portb register map .............................................................. 44 portc register map dspic33fj32mc204 and dspic33fj16mc304 .......................................... 44 power-on reset (por)....................................................... 67 power-saving features .................................................... 111 clock frequency and switching ............................... 111 program address space..................................................... 29 construction ............................................................... 51 data access from program memory using program space visibility..................................... 54 data access from program memory using table instructions ..................................... 53 data access from, address generation ..................... 52 memory map............................................................... 29 table read instructions tblrdh ............................................................. 53 tblrdl.............................................................. 53 visibility operation ...................................................... 54 program memory interrupt vector ........................................................... 30 organization ............................................................... 30 reset vector ............................................................... 30 pwm time base............................................................... 163 q quadrature encoder interface (qei)................................. 173 quadrature encoder interface (qei) module register map .............................................................. 39 r reader response............................................................. 326 registers ad1chs0 (adc1 input channel 0 select ................ 209 ad1chs123 (adc1 input channel 1, 2, 3 select)... 207 ad1con1 (adc1 control 1) .................................... 203 ad1con2 (adc1 control 2) .................................... 205 ad1con3 (adc1 control 3) .................................... 206 ? 2007-2012 microchip technology inc. ds70283k-page 323 dspic33fj32mc202/204 and dspic33fj16mc304 ad1cssl (adc1 input scan select low)................ 210 ad1pcfgl (adc1 port configuration low) ............ 210 clkdiv (clock divisor)............................................. 107 corcon (core control) ...................................... 23, 75 dfltcon (qei control)........................................... 177 i2cxcon (i2cx control) ........................................... 188 i2cxmsk (i2cx slave mode address mask) ............ 192 i2cxstat (i2cx status) ........................................... 190 icxcon (input capture x control) ............................ 153 iec0 (interrupt enable control 0) ............................... 84 iec1 (interrupt enable control 1) ............................... 86 iec3 (interrupt enable control 3) ............................... 87 iec4 (interrupt enable control 4) ............................... 88 ifs0 (interrupt flag status 0) ..................................... 79 ifs1 (interrupt flag status 1) ..................................... 81 ifs3 (interrupt flag status 3) ..................................... 82 ifs4 (interrupt flag status 4) ..................................... 83 intcon1 (interrupt control 1).................................... 76 intcon2 (interrupt control 2).................................... 78 inttreg interrupt control and status register......... 99 ipc0 (interrupt priority control 0) ............................... 89 ipc1 (interrupt priority control 1) ............................... 90 ipc14 (interrupt priority control 14) ........................... 96 ipc15 (interrupt priority control 15) ........................... 97 ipc16 (interrupt priority control 16) ........................... 97 ipc18 (interrupt priority control 18) ........................... 98 ipc2 (interrupt priority control 2) ............................... 91 ipc3 (interrupt priority control 3) ............................... 92 ipc4 (interrupt priority control 4) ............................... 93 ipc5 (interrupt priority control 5) ............................... 94 ipc7 (interrupt priority control 7) ............................... 95 nvmcon (flash memory control) ............................. 57 nvmkey (nonvolatile memory key) .......................... 58 ocxcon (output compare x control) ..................... 158 osccon (oscillator control) ................................... 105 osctun (frc oscillator tuning) ............................ 109 p1dc2 (pwm duty cycle 2)..................................... 172 p1dc3 (pwm duty cycle 3)..................................... 172 pdc1 (pwm duty cycle 1)....................................... 172 pllfbd (pll feedback divisor).............................. 108 pmd1 (peripheral module disable control register 1) ........................................................ 114 pmd1 (peripheral module disable control register 1) .. 114 pmd2 (peripheral module disable control register 2) ........................................................ 115 pmd3 (peripheral module disable control register 3) ........................................................ 116 pmd3 (peripheral module disable control register 3) .. 116 ptcon (pwm time base control) .......................... 163 ptmr (pwm timer count value)............................. 164 ptper (pwm time base period) ............................ 164 pwmxcon1 (pwm control 1).................................. 166 pwmxcon2 (pwm control 2).................................. 167 pxdtcon1 (dead-time control 1) .......................... 168 pxdtcon2 (dead-time control 2) .......................... 169 pxfltacon (fault a control).................................. 170 pxovdcon (override control) ................................ 171 pxsecmp (special event compare)........................ 165 qeicon (qei control).............................................. 175 rcon (reset control) ................................................ 63 spixcon1 (spix control 1)...................................... 182 spixcon2 (spix control 2)...................................... 184 spixstat (spix status and control) ....................... 181 sr (cpu status)................................................... 21, 75 t1con (timer1 control) .......................................... 145 t2con control)........................................................ 149 t3con control......................................................... 150 uxmode (uartx mode) ......................................... 195 uxsta (uartx status and control) ........................ 197 reset illegal opcode....................................................... 61, 69 trap conflict ......................................................... 68, 69 uninitialized w register ....................................... 61, 69 reset sequence ................................................................. 71 resets ................................................................................ 61 s serial peripheral interface (spi) ....................................... 179 software reset instruction (swr)...................................... 68 software simulator (mplab sim) .................................... 229 software stack pointer, frame pointer calll stack frame ................................................... 46 special features of the cpu ............................................ 211 spi module spi1 register map ..................................................... 39 symbols used in opcode descriptions ............................ 220 system control register map .............................................................. 44 t temperature and voltage specifications ac..................................................................... 244, 285 timer1 .............................................................................. 143 timer2/3 ........................................................................... 147 timing characteristics clko and i/o ........................................................... 247 timing diagrams 10-bit adc conversion (chps<1:0> = 01, simsam = 0, asam = 0, ssrc<2:0> = 000)......................... 278 10-bit adc conversion (chps<1:0> = 01, simsam = 0, asam = 1, ssrc<2:0> = 111, samc<4:0> = 00001)....................................... 278 12-bit adc conversion (asam = 0, ssrc<2:0> = 000) ........................................... 277 brown-out situations .................................................. 68 external clock .......................................................... 245 i2cx bus data (master mode) .................................. 270 i2cx bus data (slave mode) .................................... 272 i2cx bus start/stop bits (master mode)................... 270 i2cx bus start/stop bits (slave mode)..................... 272 input capture (capx) ............................................... 253 motor control pwm .................................................. 255 motor control pwm fault ......................................... 255 oc/pwm .................................................................. 254 output compare (ocx) ............................................ 253 qea/qeb input ........................................................ 256 qei module index pulse........................................... 257 reset, watchdog timer, oscillator start-up timer and power-up timer ......................................... 248 timer1, 2, 3 external clock ...................................... 250 timerq (qei module) external clock ....................... 252 timing requirements adc conversion (10-bit mode) ................................ 290 adc conversion (12-bit mode) ................................ 290 clko and i/o ........................................................... 247 external clock .......................................................... 245 input capture............................................................ 253 spix master mode (cke = 0) ................................... 286 spix module master mode (cke = 1) ...................... 286 spix module slave mode (cke = 0) ........................ 287 dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 324 ? 2007-2012 microchip technology inc. spix module slave mode (cke = 1)......................... 287 timing specifications 10-bit adc conversion requirements ...................... 279 12-bit adc conversion requirements ...................... 277 i2cx bus data requirements (master mode) ........... 271 i2cx bus data requirements (slave mode) ............. 273 motor control pwm requirements ........................... 255 output compare requirements ................................ 253 pll clock.......................................................... 246, 285 qei external clock requirements ............................ 252 qei index pulse requirements................................. 257 quadrature decoder requirements .......................... 256 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ......................................... 249 simple oc/pwm mode requirements ..................... 254 timer1 external clock requirements ....................... 250 timer2 external clock requirements ....................... 251 timer3 external clock requirements ....................... 251 u uart module uart1 register map.................................................. 39 universal asynchronous receiver transmitter (uart) ... 193 using the rcon status bits............................................... 69 v voltage regulator (on-chip) ............................................ 215 w watchdog time-out reset (wdtr).................................... 68 watchdog timer (wdt)............................................ 211, 216 programming considerations ................................... 216 www address ................................................................. 325 www, on-line support ....................................................... 7 ? 2007-2012 microchip technology inc. ds70283k-page 325 dspic33fj32mc202/204 and dspic33fj16mc304 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 326 ? 2007-2012 microchip technology inc. reader response it is our intention to provide you with the best document ation possible to ensure succe ssful use of your microchip product. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds70283k dspic33fj32mc202/204 and dspic33fj16mc304 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2007-2012 microchip technology inc. ds70283k-page 327 dspic33fj32mc202/204 and dspic33fj16mc304 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . architecture: 33 = 16-bit digital signal controller flash memory family: fj = flash program memory, 3.3v product group: mc2 = motor control family mc3 = motor control family pin count: 02 = 28-pin 04 = 44-pin temperature range: i = -40 c to+85 c (industrial) e=-40 c to+125 c (extended) h=-40 c to+150 c (high) package: sp = skinny plastic dual in-line - 300 mil body (spdip) so = plastic small outline - wide - 7.50 mil body (soic) ss = plastic shrink small outline - 5.3 mm body (ssop) ml = plastic quad, no lead package - 8x8 mm body (qfn) pt = plastic thing quad flatpa ck - 10x10x1 mm body (tqfp) mm = plastic quad, no lead package - 6x6 mm body (qfn-s) examples: a) dspic33fj32mc202te/sp: motor control dspic33, 32 kb program memory, 28-pin, extended temp., spdip package. microchip trademark architecture flash memory family program memory size (kb) product group pin count temperature range package pattern dspic 33 fj 32 mc2 02 t e / sp - xxx tape and reel flag (if applicable) dspic33fj32mc202/204 and dspic33fj16mc304 ds70283k-page 328 ? 2007-2012 microchip technology inc. notes: ? 2007-2012 microchip technology inc. ds70283k-page 329 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-335-3 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality ? management ? ? ? ? by ? dnv ? == iso/ts ? 16949 ? == ? ds70283k-page 330 ? 2007-2012 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland 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